pnx8511 NXP Semiconductors, pnx8511 Datasheet - Page 10

• Manufacturer Part Number: pnx8511
• Description: Analog Companion Chip
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12612
Product data
7.1.2 Video input modes
If the interface is operated in D1 mode, the data stream presented to the interface has
to be D1 compliant i.e., the maximum and minimum codes (8-bit 0x00 0xFF, 10-bit
0x000 0x3FF) must not occur during active video.
A detailed description of video input data formats can be found in
video modes listed correspond to the settings of the DEMUX_MODE bits in the
register 0x95 VMUXCTL
equivalent to the processing and the video DAC operation frequency the appropriate
divider registers in the audio/clock register section have to be programmed. As a
general rule the settings in
Table 10:
The PNX8510/11 video interface supports a wide variety of video formats. The video
interface is designed in a generic fashion. It is de-coupled from the actual video data
paths in the system and imposes only a few restrictions on the video data streams
provided to the chip.
This section explains the possible video stream formats and provides details on
synchronizing the PNX8510/11 with respect to a particular video data format.
The PNX8510/11 accepts the video formats shown in
single interface with up to 81 MHz interface clock:
YUV 4:2:2
This is the CCIR-656 compliant format and will mainly be used at an interface speed
of 27 MHz to feed the video encoder modules in the chip.
This is the standard interface format for the secondary video encoder pipeline unless
the chip is used in High Definition (HD) mode.
The YUV 4:2:2 format can also be used to feed the HD data path as long as the pixel
clock rate stays below 81 MHz. To operate the HD data path with 4:2:2 source
material the 4:2:2 to 4:4:4 filter should be enabled to achieve the best video quality.
Mode
4:2:2 YUV SD Single Interface Mode
4:4:4 RGB 2FH Single Interface Mode
4:2:2 YUV 1080i Double Interface Mode
Fig 4. YUV 4:2:2
FF
00
Clock frequency settings
00 EAV 80
Rev. 04 – 12 January 2004
10
Section
Table 10
80
10
8.1. If the video interface clock frequency is not
should be used:
FF
Interface
clock
27 MHz
81 MHz
74.25 MHz
00
00 SAV U1
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Figure 4
Processing
clock
27 MHz
27 MHz
74.25 MHz
Y1
PNX8510/11
Analog companion chip
V1
to
Figure 10
Y2
Section
U3
DAC clock
27 MHz
27 MHz
74.25 MHz
Y3
7.1.2. The
MDB638
on a
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