pnx8510 NXP Semiconductors, pnx8510 Datasheet - Page 39

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pnx8510

Manufacturer Part Number
pnx8510
Description
Analog Companion Chip
Manufacturer
NXP Semiconductors
Datasheet

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Product data
7.7 Test mode
This section describes how the analog test modes are implemented in the
PNX8510/11. Note that these test modes are intended for production test only. The
chip needs to be brought into analog test mode via the JTAG boundary scan
controller. Once the chip is in analog test mode the different test modes can be
enabled via the GPIO pins. The data input for the video DACs is provided via the DV1
interface for DACs 1 through 4 and via the DV2 interface for DACs 5 and 6
respectively. The “main switch” for the test mode is controlled by the JTAG boundary
scan controller. Once the chip is in analog test mode, the GPIO pins can be used to
select certain combinations outlined in the tables.
Table 26:
For the video DACs 1 to 4, the primary 10-bit D1 interface (DV1_IN[9:0]) provides the
10-bit input. Video DACs 5 and 6 are stimulated through the secondary D1 interface
(DV2_IN[9:0])
Table 27:
The serial audio data streams for the first stereo pair are provided through the
I2S_IN1_SD and the I2S_IN1_WS pins. The audio DAC pair 3 and 4 get their serial
data through pins I2S_IN2_SD and I2S_IN2_WS.
GPIO2
0
0
1
1
GPIO4
0
0
1
1
Fig 30. Clocks audio submodule
Video DAC test modes
Audio DAC test modes
GPIO5
0
1
0
1
GPIO3
0
1
0
1
Rev. 04 – 12 January 2004
i2s_aos_clk
Test
ADAC1/2 and ADAC3/4 stereo pair first and second channel off
ADAC1/2 stereo pair first channel active
ADAC3/4 stereo pair second channel active
ADAC1/2 and ADAC3/4 stereo pair first and second channel active
sck_in
test_a
Test
VDAC1 and VDAC5 active
VDAC2 and VDAC6 active
VDAC3 and VDAC5 active
VDAC4 and VDAC6 active
ws_in
sel_a
4-BIT DIVIDER
9-BIT DIVIDER
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
MDB658
PNX8510/11
Analog companion chip
clk_a
sclk_a
ws_a
39 of 92

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