pnx8510 NXP Semiconductors, pnx8510 Datasheet - Page 14

• Manufacturer Part Number: pnx8510
• Description: Analog Companion Chip
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12612
Product data
7.1.4 Video DAC control
7.1.5 VBI data
The PNX8510/11 contains six video DACs, four dedicated to the primary video
pipeline and two to the secondary video processing path.
The first DAC of the primary video channel (VOUT1) is always assigned to the
primary standard definition data path. The output of the DAC can be changed from
CVBS to Y by resetting the CVBSEN bit of the register DACCTRL (offset 0x2D) to
zero.
The second DAC of the primary video channel (VOUT2) is assigned to either the
standard definition (SD) data path or High Definition (HD) data path. In the SD mode,
it carries the chrominance, C (Y/C operation) if the CEN bit in the DACCTRL (offset
0x2D) is set or the Red/V channel (RGB/Component mode operation) if the CEN bit
of the DACCTRL (offset 0x2D) is reset. In HD mode (SD_HD bit of INPCTL register,
offset 0x3A is set to zero) this DAC carries either the Red channel or the Y channel
depending on whether the HD path is operated in RGB or YUV mode. Note that the
CEN bit must be reset for HD operation.
The third DAC of the primary video channel (VOUT3) is also assigned to either the
standard definition (SD) data path or High Definition (HD) data path. In SD mode, it
carries the luminance channel if the VBSEN bit in the DACCTRL (offset 0x2D) is set
or the Green/Y channel if the VBSEN bit is reset (RGB/Component mode operation).
If the high definition data path is operational (SD_HD=1’b0) this DAC carries the
Green or U channel depending on whether the HD path is operated in YUV or RGB
mode.
The configuration of the fourth DAC in the primary video data path (VOUT4) can not
be changed with a programming register. This DAC carries the Blue or U channel in
standard definition mode and the Blue or V channel if the high definition data path is
active.
The configuration of the DACs for the secondary video data path is limited to the
CVBS/Y DAC (VOUT5). If the CVBSEN bit in the DACCTRL register (offset 0x2D) is
set, this DAC carries the CVBS signal. Resetting the bit results in the Y signal being
assigned to this DAC.
The second DAC of the secondary video pipeline (VDAC6) always carries the
chrominance signal.
VBI data extraction from a D1 data stream is only supported for standard definition
formats. The extraction follows the concept of Philips video decoders, such as the
SAA7114. Both video interfaces can carry VBI data information. The content of the
VBI data is entirely determined by the source decoder chip software driver.
The PNX8510/11 supports two VBI data streams. The limitation to two VBI data
streams implies certain limitations when using multiple PNX8510/11 chips in a
system. In this case one PNX8510/11 gets either one or two (all) VBI data streams.
The other PNX8510/11 IC would get one or none.
Only the ANC/SAV-EAV header style VBI data encoding mode is supported in the
PNX8510/11. According to these standards VBI data is always inserted in the
horizontal blanking interval of a line. The data is preceded by an ANC header which is
Rev. 04 – 12 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PNX8510/11
Analog companion chip
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