pnx8526 NXP Semiconductors, pnx8526 Datasheet - Page 5

• Manufacturer Part Number: pnx8526
• Description: Programmable Source Decoder With Integrated Peripherals
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 15101
Product data sheet
Table 2:
# indicates multiplexed signal, see
Symbol
PCI_AD[21]
PCI_AD[20]
PCI_AD[19]
PCI_AD[18]
PCI_AD[17]
PCI_AD[16]
PCI_AD[15]
PCI_AD[14]
PCI_AD[13]
PCI_AD[12]
PCI_AD[11]
PCI_AD[10]
PCI_AD[9]
PCI_AD[8]
PCI_AD[7]
PCI_AD[6]
PCI_AD[5]
PCI_AD[4]
PCI_AD[3]
PCI_AD[2]
PCI_AD[1]
PCI_AD[0]
PCI_CBE[3]
PCI_CBE[2]
PCI_CBE[1]
PCI_CBE[0]
CLK
PCI_DEVSEL
PCI_FRAME
PCI_GNT
PCI_GNT_A
Peripheral Controller Interface (PCI)
Pin
AE4
AD4
AE5
AD5
AC5
AC6
AD8
AC8
AF9
AE9
AD9
AC9
AF10 I/O
AE10 I/O
AC10 I/O
AF11 I/O
AE11 I/O
AD11 I/O
AC11 I/O
AE12 I/O
AD12 I/O
AC12 I/O
AD1
AF5
AE8
AD10 I/O
AA1
AF7
AF6
Y3
Y4
Rev. 02 — 11 July 2005
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
Programmable source decoder with integrated peripherials
Section 6.2.1
Description
multiplexed address or data bit 21
multiplexed address or data bit 20
multiplexed address or data bit 19
multiplexed address or data bit 18
multiplexed address or data bit 17
multiplexed address or data bit 16
multiplexed address or data bit 15
multiplexed address or data bit 14
multiplexed address or data bit 13
multiplexed address or data bit 12
multiplexed address or data bit 11
multiplexed address or data bit 10
multiplexed address or data bit 9
multiplexed address or data bit 8
multiplexed address or data bit 7
multiplexed address or data bit 6
multiplexed address or data bit 5
multiplexed address or data bit 4
multiplexed address or data bit 3
multiplexed address or data bit 2
multiplexed address or data bit 1
multiplexed address or data bit 0
multiplexed command or byte enable 3
multiplexed command or byte enable 2
multiplexed command or byte enable 1
multiplexed command or byte enable 0
PCI bus clock
device select is asserted when a target address is
decoded and remains asserted to indicate that a
target device is selected
frame is asserted to indicate start of bus
transaction and remains asserted until final data
phase begins
arbitration grant is asserted to indicate access to
the bus has been granted; this pin is an input
when an external arbiter is used and an output
when using the internal arbiter
auxiliary arbitration PCI_GNT_A is asserted to
indicate bus access has been granted to an
external PCI master; used where internal arbiter is
configured
for more details.
…continued
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
PNX8526
Alternate
function
#
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