clc408 ETC-unknow, clc408 Datasheet - Page 5

• Manufacturer Part Number: clc408
• Description: High-speed, Low-power Line Driver
• Manufacturer: ETC-unknow

Standard op amp circuits work with CFB op amps.
There are 3 unique design considerations for CFB:
The following sub-sections cover:
DC Gain (non-inverting)
The non-inverting DC voltage gain for the configuration
shown in Figure 1 is:
The normalized gain plots in the Typical Performance
Characteristics section show different feedback
resistors (R
recommended for obtaining the highest bandwidth with
minimal peaking. The resistor R
the non-inverting input.
For A
values to calculate the recommended value of R
A
Select R
DC gain accuracy is usually limited by the tolerance of
R
DC Gain (unity gain buffer)
The recommended R
is left open. Parasitic capacitance at the inverting node
may require a slight increase of R
frequency response.
v
f
and R
≥ 6, the minimum recommended R
v
The feedback resistor (R
AC performance
R
The output offset voltage is not reduced by
balancing input resistances
Design parameters, formulas and techniques
Interfaces
Application circuits
Layout techniques
SPICE model information
< 6, use linear interpolation on the nearest A
V
g
f
g
in
cannot be replaced with a short or a capacitor
.
to set the DC gain:
f
Figure 1: Non-Inverting Gain
) for different gains. These values of R
R
t
R
3
2
g
f
CLC408
+
-
for unity gain buffers is 3k . R
A
V
V
v
CC
EE
7
4
1
6.8 F
0.1 F
0.1 F
6.8 F
+
R
R
f
R
6
CLC408 DESIGN INFORMATION
R
+
g
g
t
f
f
provides DC bias for
in Figures 1-3) sets
f
A
to maintain a flat
R
v
f
f
is 200 .
1
V
o
f
. For
f
are
v
g
5
DC Gain (inverting)
The inverting DC voltage gain for the configuration
shown in Figure 2 is:
The normalized gain plots in the Typical Performance
Characteristics section show different feedback
resistors (R
recommended for obtaining the highest bandwidth with
minimal peaking. The resistor R
the non-inverting input.
For |A
values to calculate the recommended value of R
|A
Select R
R
This can be solved by driving R
buffer like the CLC111, or increasing R
the AC Design (small signal bandwidth) sub-section
for the tradeoffs.
DC gain accuracy is usually limited by the tolerance of
R
DC Gain (transimpedance)
Figure 3 shows a transimpedance circuit where the
current I
source’s output resistance is much greater than R
The DC transimpedance gain is:
The recommended R
the inverting node may require a slight increase of R
maintain a flat frequency response.
DC gain accuracy is usually limited by the tolerance
of R
g
f
v
and R
| ≥ 6, the minimum recommended R
becomes small and will load the previous stage.
f
.
v
| < 6, use linear interpolation on the nearest A
in
V
g
g
in
.
to set the DC gain:
is injected at the inverting node. The current
f
) for different gains. These values of R
R
Figure 2: Inverting Gain
t
3
2
f
CLC408
-
+
is 3k . Parasitic capacitance at
A
V
V
CC
EE
v
7
4
6.8 F
0.1 F
0.1 F
6.8 F
R
+
R
R
R
g
f
6
+
g
g
f
t
with a low impedance
provides DC bias for
A
R
A
R
f
v
http://www.national.com
. At large gains,
f
f
V
I
in
is 200 .
and R
o
V
o
R
g
f
. See
f
. For
f
are
f
to
f
v
.