pef80913 Infineon Technologies Corporation, pef80913 Datasheet - Page 79

• Manufacturer Part Number: pef80913
• Description: 2b1q Second Gen. Modular Isdn Nt
• Manufacturer: Infineon Technologies Corporation

Table 15
Reporting and execution of maintenance information is only sensible if the Q-SMINT I
is synchronous. Filters are provided to avoid meaningless reporting.
Reset values are applied to the maintenance bits before the state machine enters one of
the states in
2.4.2.4
Since the maintenance data must be put into and read from the U-frame in time there is
the need for synchronization if M-Bit data is exchanged via the µC-interface. Below the
timing is given for the access to the M-Bit read and write registers.
The write access timing is depicted in
are the 6 ms and 12 ms interrupts which are accommodated in the ISTAU register. An
active 6 ms interrupt signals that from this event there is a time frame of 3 basic frames
duration (4.5 ms) for the write access to the EOCW register.
The 12 ms interrupt serves as time reference for the write access to the M4W and M56W
registers. From the point of time the 12 ms interrupt goes active there is a time window
of 7 basic frames to overwrite the register values. The programmed data will be sent out
with the next U-superframe.
Note that the point of time when the 6 ms and 12 ms interrupts are generated within basic
frame #1 and #5 is not fixed and may vary.
Data Sheet
Pend. Deac. S/T
Pend. Deac. U
Analog Loop Back
M-Bit Register Access Timing
Table
Enabling the Maintenance Channel (Receive Direction)
15.
Figure
65
36. Timing references for a write access
Functional Description
PEF 82912/82913
2001-03-30