pef80913 Infineon Technologies Corporation, pef80913 Datasheet - Page 170

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pef80913

Manufacturer Part Number
pef80913
Description
2b1q Second Gen. Modular Isdn Nt
Manufacturer
Infineon Technologies Corporation
Datasheet
4.7.5
SQRR
Value after reset: 00
MSYN
MFEN
SQR1-4
4.7.6
SQXR
Value after reset: 00
Data Sheet
MSYN
7
7
0
SQRR - S/Q-Channel Receive Register
SQXR- S/Q-Channel Transmit Register
0 =
1 =
Multi-frame Synchronization State
0 =
1 =
Multiframe Enable
Read-back of the MFEN bit of the SQXR register
0 =
1 =
Received S/Q Bits
Received Q bits in frames 1, 6, 11 and 16
MFEN
MFEN
Analog loop is open
Analog loop is closed internally or externally according to the EXLP
bit in the S_CONF0 register
The S/T receiver has not synchronized to the received F
bits
The S/T receiver has synchronized to the received F
S/T multiframe is disabled
S/T multiframe is enabled
H
H
0
0
0
0
read
write
156
SQR1
SQX1
SQR2
SQX2
Register Description
PEF 82912/82913
SQR3
SQX3
Address:
Address:
A
and M bits
A
2001-03-30
and M
SQR4
SQX4
0
0
35
35
H
H

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