mk50n512cmd100 Freescale Semiconductor, Inc, mk50n512cmd100 Datasheet - Page 14

• Manufacturer Part Number: mk50n512cmd100
• Description: K50 Sub-family Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

General
5.1.4 Power mode transition operating behaviors
All specifications except t
assume this clock configuration:
1. Normal boot (FTFL_OPT[LPBOOT]=1)
14
Symbol
• CPU and system clocks = 100 MHz
• Bus and FlexBus clocks = 50 MHz
• Flash clock = 25 MHz
t
POR
After a POR event, amount of time from the point V
reaches 1.8V to execution of the first instruction
across the operating temperature range of the chip.
RUN → VLLS1 → RUN
RUN → VLLS2 → RUN
RUN → VLLS3 → RUN
RUN → LLS → RUN
RUN → STOP → RUN
RUN → VLPS → RUN
Description
• RUN → VLLS1
• VLLS1 → RUN
• RUN → VLLS2
• VLLS2 → RUN
• RUN → VLLS3
• VLLS3 → RUN
• RUN → LLS
• LLS → RUN
• RUN → STOP
• STOP → RUN
• RUN → VLPS
• VLPS → RUN
Table 5. Power mode transition operating behaviors
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
POR
, and VLLSx→RUN recovery times in the following table
Preliminary
DD
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
123.8
Max.
49.3
49.2
300
4.1
4.1
4.1
4.1
5.9
4.1
4.2
4.1
5.8
Freescale Semiconductor, Inc.
Unit
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
Notes
1