mk5027 STMicroelectronics, mk5027 Datasheet - Page 3

• Manufacturer Part Number: mk5027
• Description: Ss7 Signalling Link Controller
• Manufacturer: STMicroelectronics

Table 1: Pin Description (continued)
Signal Name
BUSAKO
BUSRQ
HOLD
HLDA
BM1
ALE
AS
Pin(s)
16
17
18
19
IO/OD
Type
O/3S
O/3S
I
Pins 15 and 16 are programmable though bit 00 of CSR4 (BCON).
If CSR4<00> BCON = 0,
BYTE MASK<1:0> indicates the byte(s) on the DAL to be read or written
during this bus transaction. MK5027 drives these lines only as a Bus
Master. MK5027 ignores the BM lines when it is a Bus Slave.
Byte selection is done as outlined in the following table.
If CSR4<00>BCON = 1,
Byte selection is done using the BYTE line and DAL<00> latched during
the address portion of the bus transaction. MK5027 drives BYTE only a
Bus Master and ignores it when a Bus Slave. Byte selection is done as
outlined in the following table.
BUSAKO is a bus request daisy chain output. If MK5027 is not requesting
the bus and it receives HLDA, BUSAKO will be driven low. If MK5027 is
requesting the bus when it receives HLDA, BUSAKO will remain high.
Note: All transfers are entire word unless the MK5027 is configured for 8
bit operation.
Pins 17 is configured through bit 0 of CSR4.
If CSR4<00> BCON = 0,
HOLD request is asserted by MK5027 when it requires a DMA cycle, if
HLDA is inactive, regardless of the previous state of the HOLD pin.
HOLD is held low for the entire ensuing bus transaction.
If CSR4<00> BCON = 1,
BUSRQ is asserted by MK5027 when it requires a DMA cycle if the prior
state of the BUSRQ pin was high and HLDA is inactive. BUSRQ is held
low for the entire ensuing bus transaction.
The active level of ADDRESS STROBE is programmable through CSR4.
The address portion of a bus transfer occurs while this signal is at its
asserted level. This signal is driven by MK5027 while it is the BUS
MASTER. At all other times, the signal is tristated.
If CSR4<01> ACON = 0,
ADDRESS LATCH ENABLE is used to demultiplex the DAL lines and define
the address portion of the transfer and remains low during the data portion.
If CSR4<01> ACON = 1,
As AS, the signal pulses low during the address portion of the bus
transfer. The low to high transition of AS can be used by a slave device to
strobe the address into a register.
AS is effectively the inversion of ALE.
HOLD AKNOWLEDGE is the response to HOLD. When HLDA is low in response
to MK5027’s assertion of HOLD, the MK5027 is the Bus Master. HLDA should be
desasserted ONLY after HOLD has been released by the MK5027.
I/O PIN 15 = BMO (O/3S)
I/O PIN 16 = BM1 (O/3S)
BM1
LOW
LOW
HIGH
HIGH
I/O PIN 15 = BYTE (O/3S)
I/O PIN 16 = BUSAKO(O)
BYTE
LOW
LOW
HIGH
HIGH
I/O PIN 17 = HOLD
I/O PIN 17 = BUSRQ
I/O PIN 18 = ALE
I/O PIN 18 = AS
BM0
LOW
HIGH
LOW
HIGH
DAL<00>
LOW
HIGH
LOW
HIGH
TYPE OF TRANSFER
ENTIRE WORD
UPPER BYTE (DAL<15:08>)
LOWER BYTE (DAL<07:00>)
NONE
TYPE OF TRANSFER
ENTIRE WORD
ILLEGAL CONDITION
LOWER BYTE
UPPER BYTE
Descriplion
MK5027
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