mk5027 STMicroelectronics, mk5027 Datasheet
mk5027
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mk5027 Summary of contents
Page 1
... DMA chip would han- dle data for only a single block at a time.) The MK5027 may be used with any of several popular 16 and 8 bit microprocessors, such as 68000, 6800, Z8000, Z80, LSI-11, 8086, 8088, 8080, etc. ...
Page 2
... DAL external bus transceiver control line. DALI is driven by the MK5027 only while it is the BUS MASTER. DALI is asserted by the MK5027 when | ads from the DAL lines during the data portion of a READ transfer. DALI is not asserted during a WRITE transfer. DAL OUT is an external bus transceiver control line. DALO is driven by the MK5027 only while it is the BUS MASTER ...
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... UPPER BYTE BUSAKO is a bus request daisy chain output. If MK5027 is not requesting the bus and it receives HLDA, BUSAKO will be driven low. If MK5027 is requesting the bus when it receives HLDA, BUSAKO will remain high. Note: All transfers are entire word unless the MK5027 is configured for 8 bit operation ...
Page 4
... WRITE cycle or that memory has put data on the DAL lines in a READ cycle bus Slave, the MK5027 asserts READY when it has put data on the DAL lines during a READ cycle or is about to take data from the DAL lines during WRITE cycle. READY is a response to DAS and it will be released after DAS negated ...
Page 5
... Figure 2: Possible System Configuration for the MK5027. MK5027 5/19 ...
Page 6
... DMA: one channel for receive and one chan- nel for transmit. The MK5027 handles error recov- ery and link status signalling. The MK5027 is intended to be used with any popular bit microprocessor. Possible sys- tem configuration for the MK5027 is shown in Fig- ure 2 ...
Page 7
... MK5027 is allowed and commanded to transmit the buffer When the MK5027 does not own the buffer, it will not transmit that buffer. For receive. when the MK5027 owns a buffer. it may place received data into that buffer. Conversely. when the MK5027 does not own a receive buff- er, it will not place received data in that buffer ...
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... MK5027 Figure 4: MK5027 Buffer Management. CSR 2, CSR3 POINTER TO INITIALIZATI ON BLOCK INITIALIZATI ON BLOCK MODE FRAME ADDRESS FIELDS TIMER VALUES RX DESCRIPTOR POINTER TX DESCRIPTOR POINTER XID/TEST TRANSMIT DESCRIPTOR POINTER XID/TES T RECEIVE DESCRI PTOR POINTER STAT US BUFFER ADDRESS ERROR COUNTERS STATUS BUFFER XID/TEST RECEIVE BUFFER ...
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... SIGNALLING UNIT REPERTOIRE The signal unit repertoire of the MK5027 is shown in Table 1. This set conforms to the 1988 CCITT specification for level 2 of Signalling System #7. The definitions for the symbols for the frame types are: Table 1: MK5027 Signal Unit Repertoire. MK5027 Name Definition ...
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... MK5027 MK5027 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Temperature under Bias Storage Temperature Voltage on Any Pin with Respect to Ground Power Dissipation Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the above device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied ...
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... Data setup time to the falling edge of SWDS DAS (bus slave write) 39 ALE T ALE width high ALEW 40 ALE T Delay from rising edge od DAS to DSW the rising edge of ALE 41 DAS T DAS width low DSW MK5027 Test Min. Typ. Max. Conditions 140 ...
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... MK5027 AC TIMING SPECIFICATIONS (Continued +5V 5 percent, unless otherwise specified Signal Symbol Parameter 42 DAS T Delay from the falling edge of ALE to ADAS the falling edge of DAS 43 DAS T Delay from the rising edge of DALO RIDF to the falling edge of DAS (bus ...
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... Figure 5A: TTL Output Load Diagram. TEST POINT FROM OUTPUT UNDER TEST 0 NOTE: This load is used on all outputs except INTR, HOLD, READY. Figure 6: MK5027 Serial Link Timing Diagram RCLK RD TCLK 12 TD TIMING MEASUREMENTS ARE MADE AT THE FOLLOWING VOLTAGES, UNLESS OTHERWISE SPECIFIED: OUTPUT INPUT FLOAT Figure 5B: Open Drain Output Load Diagram ...
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... MK5027 Figure 7: MK5027 Bus Master Timing Diagram (read). Note: The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device return READY. 14/19 ...
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... Figure 8: MK5027 Bus Master Timing Diagram (write). Note: The Bus Master cycle time will increase from a minimum of 600ns in 100ns steps until the slave device return READY. MK5027 15/19 ...
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... MK5027 Figure 9: MK5027 Bus Slave Timing Diagram (read) Figure 10: MK5027 Bus Slave Timing Diagram (write) 16/19 ...
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... DIP48 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. a1 0.63 b 0.45 b1 0. 15.2 e 2.54 e3 58. 4.445 L 3.3 inch MAX. MIN. TYP. 0.025 0.018 0.31 0.009 0.050 62.74 16.68 0.598 0.100 2.300 14.1 0.175 0.130 MK5027 MAX. 0.012 2.470 0.657 0.555 17/19 ...
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... MK5027 PLCC52 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. A 4.20 A1 0.51 A3 2.29 B 0.33 B1 0.66 C 0.25 D 19.94 D1 19.05 D2 17.53 D3 15.24 E 19.94 E1 19.05 E2 17.53 E3 15.24 e 1.27 L 0.64 L1 1.53 M 1.07 M1 1.07 18/19 inch MAX. MIN. TYP. 5.08 0.165 0.020 3.30 0.090 0.53 0.013 0.81 0.026 0.01 20.19 0.785 19.20 0.750 18.54 0.690 0.60 20.19 0.785 19.20 0.750 18.54 0.690 0.60 0.05 0.025 0.060 1.22 0.042 1.42 0.042 MAX. 0.20 0.13 0.021 0.032 0.795 0.756 ...
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... SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics – Printed in Italy – All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Swit zerland - Taiwan - Thailand - United Kingdom - U.S.A. MK5027 19/19 ...