W233 Cypress Semiconductor Corp., W233 Datasheet - Page 2

• Manufacturer Part Number: W233
• Description: Spread Spectrum FTG For Via Mobile K7 Chipset
• Manufacturer: Cypress Semiconductor Corp.

Pin Definitions
Document #: 38-07250 Rev. **
CPUC0_F,
CPUT0_F,
CPU_CS
PCI1:6
FS1/PCI0
FS2/PCI_F
STOP_CLK#
48MHz/FS0
SEL24_48#/24_
48MHz
REF1
REF2/FS3
REF0_2X
SDRAMIN
SDRAM0:5,
SDRAM_F
SCLK
SDATA
X1
X2
SDRAM_STOP#
Pin Name
32, 29, 28, 27
8, 9, 10, 11,
37, 36, 33,
Pin No.
40, 41
12, 15
38
22
23
47
46
48
18
26
25
16
42
5
4
2
3
Pin Type
(open-
drain)
PRELIMINARY
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
CPU Clock Output 0: CPUT0_F and CPUC0_F are the differential CPU clock
outputs for the K7 processor.
CPU Clock Output for Chipset: CPU_CS is the push-pull clock output for the
chipset. It has the same phase relationship as CPUT0_F.
PCI Clock Outputs 1 through 6: These six PCI clock outputs are controlled
by the PCI_STP# control pin. Frequency is set by FS0:3 inputs or through serial
input interface, see Tables 1 and 5 for details. Output voltage swing is con-
trolled by voltage applied to VDDQ3.
Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set
by FS0:3 inputs or through serial input interface. This pin also serves as a
PCI_STP# strap option to determine device operating frequency as described
in Table 1.
Fixed PCI Clock Output/Frequency Select 2: As an output, frequency is set
by the FS0:3 inputs or through serial input interface, see Tables 1 and 5. This
output is controlled by the STOP_CLK# input. This pin also serves as a power-
on strap option to determine device operating frequency as described in Table
2.
STOP_CLK# Input: LVTTL-compatible input that places the device in stop-
clock mode when held LOW. In stop-clock mode, CPUT0_F and CPUC0_F will
be active and all the other output clocks will be driven LOW. STOP_CLK# is an
asynchronous input. W233 will not complete the current clock cycle when
STOP_CLK# is being driven LOW.
48-MHz Output/Frequency Select 0: 48 MHz is provided in normal operation.
In standard PC systems, this output can be used as the reference for the
Universal Serial Bus host controller. This pin also serves as a power on strap
option to determine device operating frequency as described in Table 1.
24_48-MHz Output/Frequency Select 24 or 48 MHz: In standard PC sys-
tems, this output can be used as the clock input for a Super I/O chip. The output
frequency is controlled by Configuration Byte 3 bit[6] or SEL 24_48 MHz stop
option. The default output frequency is 24 MHz. This pin also serves as a
power-on strap option to determine device operating frequency.
Reference Clock Output 1: 3.3V 14.318-MHz output clock.
Reference Clock Output 2/Frequency Select 3: 3.3V 14.318-MHz output
clock. This pin also serves as a power-on strap option to determine device
operating frequency.
Reference Clock Output 0: 3.3V 14.318-MHz output clock with double drive
strength.
Buffered Input Pin: The signal provided to this input pin is buffered to seven
outputs (SDRAM0:5 & SDRAM_F).
Buffered Outputs: These seven dedicated outputs provide copies of the sig-
nal provided at the SDRAMIN input. The swing is set by VDD, and they are
deactivated when SDRAM_STOP# input is set LOW, except SDRAM_F.
Clock pin for SMBus circuitry.
Data pin for SMBus circuitry.
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal.
If using an external reference, this pin must be left unconnected.
SDRAM Stop Input: LVTTL compatible input that disables the SDRAM output
clocks, except SDRAM_F.
Pin Description
Page 2 of 16
W233