adg3308 Analog Devices, Inc., adg3308 Datasheet - Page 18

• Manufacturer Part Number: adg3308
• Description: Low Voltage 1.15 V To 5.5 V, Bidirectional, Logic Level Translators
• Manufacturer: Analog Devices, Inc.

ADG3308/ADG3308-1
APPLICATIONS
The ADG3308/ADG3308-1 are designed for digital circuits that
operate at different supply voltages; therefore, logic level transla-
tion is required. The lower voltage logic signals are connected to
the A pins, and the higher voltage logic signals to the Y pins.
The ADG3308/ADG3308-1 can provide level translation in
both directions from A
nating the need for a level translator IC for each direction. The
internal architecture allows the ADG3308/ADG3308-1 to
perform bidirectional level translation without an additional
signal to set the direction in which the translation is made. It
also allows simultaneous data flow in both directions on the
same part, for example, when two channels translate in A→Y
direction while the other two translate in Y→A direction. This
simplifies the design by eliminating the timing requirements for
the direction signal and reduces the number of ICs used for level
translation.
Figure 40 shows an application where a 3.3 V microprocessor
can read or write data to and from a 1.8 V peripheral device
using an 8-bit bus.
When the application requires level translation between a
microprocessor and multiple peripheral devices, the ADG3308/
ADG3308-1 I/O pins can be three-stated by setting EN = 0. This
feature allows the ADG3308/ADG3308-1 to share the data
buses with other devices without causing contention issues.
3.3V
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Figure 40. 1.8 V to 3.3 V 8-Bit Level Translation Circuit
H
H
H
H
H
H
H
H
1
2
3
4
5
6
7
8
100nF
→
Y or Y
ADG3308-1
ADG3308/
V
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN
CCY
→
V
GND
A on all eight channels, elimi-
CCA
A1
A2
A3
A4
A5
A6
A7
A8
100nF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
L
L
L
L
L
L
L
L
1
2
3
4
5
6
7
8
1.8V
Rev. A | Page 18 of 20
Figure 41 shows an application where a 3.3 V microprocessor is
connected to 1.8 V peripheral devices using the three-state feature.
LAYOUT GUIDELINES
As with any high speed digital IC, the printed circuit board
layout is important in the circuit overall performance. Care
should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each V
V
(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the V
tance of the high speed signal track can cause significant over-
shoot. This effect can be reduced by keeping the length of the
tracks as short as possible. A solid copper plane for the return
path (GND) is also recommended.
CCY
) should be bypassed using low effective series resistance
GND
3.3V
Figure 41. 1.8 V to 3.3 V Level Translation Circuit
CS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
H
H
H
H
H
H
H
H
1
2
3
4
5
6
7
8
Using the Three-State Feature
CCA
100nF
100nF
and V
ADG3308-1
ADG3308-1
ADG3308/
V
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN
ADG3308/
V
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
EN
CCY
CCY
CCY
V
V
GND
GND
CCA
CCA
A1
A2
A3
A4
A5
A6
A7
A8
A1
A2
A3
A4
A5
A6
A7
A8
pins. The parasitic induc-
100nF
100nF
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
pin (V
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1.8V
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1.8V
CCA
and