adg3308 Analog Devices, Inc., adg3308 Datasheet - Page 15

• Manufacturer Part Number: adg3308
• Description: Low Voltage 1.15 V To 5.5 V, Bidirectional, Logic Level Translators
• Manufacturer: Analog Devices, Inc.

TERMINOLOGY
V
Logic input high voltage at Pin A1 to Pin A8.
V
Logic input low voltage at Pin A1 to Pin A8.
V
Logic output high voltage at Pin A1 to Pin A8.
V
Logic output low voltage at Pin A1 to Pin A8.
C
Capacitance measured at Pin A1 to Pin A8 (EN = 0).
I
Leakage current at Pin A1 to Pin A8 when EN = 0 (high
impedance state at Pin A1 to Pin A8).
V
Logic input high voltage at Pin Y1 to Pin Y8.
V
Logic input low voltage at Pin Y1 to Pin Y8.
V
Logic output high voltage at Pin Y1 to Pin Y8.
V
Logic output low voltage at Pin Y1 to Pin Y8.
C
Capacitance measured at Pin Y1 to Pin Y8 (EN = 0).
I
Leakage current at Pin Y1 to Pin Y8 when EN = 0 (high
impedance state at Pin Y1 to Pin Y8).
V
Logic input high voltage at the EN pin.
V
Logic input low voltage at the EN pin.
C
Capacitance measured at EN pin.
I
Enable (EN) pin leakage current.
t
Three-state enable time for Pin A1 to Pin A8/Pin Y1 to Pin Y8.
t
Propagation delay when translating logic levels in the A
direction.
t
Rise time when translating logic levels in the A
t
Fall time when translating logic levels in the A
EN
P, A-Y
R, A-Y
F, A-Y
LA, HiZ
LY, HiZ
LEN
A
Y
EN
IHA
ILA
OHA
OLA
IHY
ILY
OHY
OLY
IHEN
ILEN
→
→
Y direction.
Y direction.
→
Y
Rev. A | Page 15 of 20
D
Guaranteed data rate when translating logic levels in the A
direction under the driving and loading conditions specified in
Table 1.
t
Difference between propagation delays on any two channels
when translating logic levels in the A
t
Difference in propagation delay between any one channel and
the same channel on a different part (under same driving/
loading conditions) when translating in the A
t
Propagation delay when translating logic levels in the Y→A
direction.
t
Rise time when translating logic levels in the Y
t
Fall time when translating logic levels in the Y
D
Guaranteed data rate when translating logic levels in the Y
direction under the driving and loading conditions specified in
Table 1.
t
Difference between propagation delays on any two channels
when translating logic levels in the Y
t
Difference in propagation delay between any one channel and
the same channel on a different part (under same driving/
loading conditions) when translating in the Y
V
V
V
V
I
V
I
V
I
V
I
V
SKEW, A-Y
PPSKEW, A-Y
P, Y-A
R, Y-A
F, Y-A
SKEW, Y-A
PPSKEW, Y-A
CCA
CCY
HiZA
HiZY
CCA
CCA
CCY
CCY
CCA
CCY
CCA
CCY
MAX, A-Y
MAX, Y-A
supply voltage.
supply voltage.
supply current.
supply current.
supply current during three-state mode (EN = 0).
supply current during three-state mode (EN = 0).
ADG3308/ADG3308-1
→
→
A direction.
Y direction.
→
→
→
→
A direction.
Y direction.
A direction.
A direction.
→
→
A
Y