cbtl06141 NXP Semiconductors, cbtl06141 Datasheet - Page 5

• Manufacturer Part Number: cbtl06141
• Description: Gen1 Display 2 1 Multiplexer
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 2.
CBTL06141
Product data sheet
Symbol
GPU_SEL
DDC_AUX_SEL
XSD
TST0
DIN1_0+
DIN1_0−
DIN1_1+
DIN1_1−
DIN1_2+
DIN1_2−
DIN1_3+
DIN1_3−
DIN2_0+
DIN2_0−
DIN2_1+
DIN2_1−
DIN2_2+
DIN2_2−
DIN2_3+
DIN2_3−
DOUT_0+
DOUT_0−
DOUT_1+
DOUT_1−
DOUT_2+
DOUT_2−
DOUT_3+
DOUT_3−
DAUX1+
DAUX1−
DAUX2+
DAUX2−
Pin description
6.2 Pin description
Ball
A1
C2
B7
G2
B4
A4
B5
A5
B6
A6
A8
A9
B8
B9
D8
D9
E8
E9
F8
F9
B2
B1
D2
D1
E2
E1
F2
F1
H9
J9
H6
J6
Type
3.3 V low-voltage CMOS
single-ended input
3.3 V low-voltage CMOS
single-ended input
3.3 V low-voltage CMOS
single-ended input
3.3 V low-voltage CMOS
single-ended input
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
differential I/O
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 July 2010
Description
Selects between two multiplexer/switch paths. When HIGH, path 2
left-side is connected to its corresponding right-side I/O. When
LOW, path 1 left-side is connected to its corresponding right-side
I/O.
Selects between DDC and AUX paths. When HIGH, the CLK and
DAT I/Os are connected to their respective DDCOUT terminals.
When LOW, the AUX+ and AUX− I/Os are connected to their
respective DDCOUT terminals.
Shutdown pin. Should be driven HIGH or connected to VDD for
normal operation. When LOW, all paths are switched off
(non-conducting) and supply current consumption is minimized.
Test pin for NXP use only. Should be tied to ground in normal
operation.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 1, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, path 2, left-side.
Four high-speed differential pairs for DisplayPort or PCI Express
signals, right-side.
High-speed differential pair for AUX signals, path 1, left-side.
High-speed differential pair for AUX signals, path 2, left-side.
Gen1 display 2 : 1 multiplexer
CBTL06141
© NXP B.V. 2010. All rights reserved.
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