cbtl06141 NXP Semiconductors, cbtl06141 Datasheet
cbtl06141
Available stocks
Related parts for cbtl06141
cbtl06141 Summary of contents
Page 1
... AUX and DDC I/Os are on separate pins of the display source device. The CBTL06141 is designed for Gen1 speeds, at 2.5 Gbit/s for PCI Express or 2.7 Gbit/s for DisplayPort, and for inputs voltages 3.3 V typical. It consumes very low current in operational mode (less than 1 mA typical) and provides for a shutdown function (less than 10 μ ...
Page 2
... Package Name Description TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 5 × 5 × 0.8 mm All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer [1] © NXP B.V. 2010. All rights reserved. Version SOT918 ...
Page 3
... DDC_DAT2 0 HPD_1 1 HPD_2 GPU_SEL DDC_AUX_SEL TST0 XSD Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer VDD 4 DOUT_n+ DOUT_n− AUX+ or SCL AUX+ AUX− AUX− or SDA HPDIN GND 002aad554 © ...
Page 4
... DOUT_2+ DOUT_3+ TST0 AUX+ HPD_2 GND HPD_1 VDD Transparent top view Ball mapping All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer CBTL06141EE 002aad360 Transparent top view DIN1_1− ...
Page 5
... High-speed differential pair for AUX signals, path 1, left-side. High-speed differential pair for AUX signals, path 2, left-side. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer © NXP B.V. 2010. All rights reserved ...
Page 6
... H7 7. Functional description Refer to The CBTL06141 uses a 3.3 V power supply. All main signal paths are implemented using high-bandwidth pass-gate technology and are non-directional. No clock or reset signal is needed for the multiplexer to function. The switch position for the main channels is selected using the select signal GPU_SEL. ...
Page 7
... Shutdown function The CBTL06141 provides a shutdown function to minimize power consumption when the application is not active but power to the CBTL06141 is provided. Pin XSD (active LOW) puts all channels in off mode (non-conducting) while reducing current consumption to near-zero. Table 6. XSD 0 1 CBTL06141 ...
Page 8
... CMOS inputs other inputs HPD, DDC inputs ambient temperature operating in free air Section 11.1 “Special considerations”. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer Min Max −0.3 +5 −40 +85 [1] - 8000 ...
Page 9
... Hz ≤ f ≤ 1.0 GHz −3.0 dB intercept −5.0 dB intercept from left-side port to right-side port or vice versa intra-pair inter-pair All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer Min Typ = ...
Page 10
... kΩ series resistor 5 from HPDIN to HPD_x or vice versa Conditions = 3.6 V; 0.3 V ≤ All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer Min Typ Max −0 −0.3 - +5.0 3 ...
Page 11
... Certain cable or dongle misplug scenarios make it possible for input condition to occur on pins AUX+ and AUX−, as well as HPDIN. When AUX+ and AUX− are connected through a minimum of 2.2 kΩ each, the CBTL06141 will sink current but will not be damaged. Similarly, HPDIN may be connected via at least a 1 kΩ resistor. (Correct functional operation to specification is not expected in these scenarios ...
Page 12
... 5.1 5.1 0 0.15 4.9 4.9 REFERENCES JEDEC JEITA MO-195 - - - All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer detail 0.05 0.08 0.1 EUROPEAN PROJECTION SOT918-1 y ...
Page 13
... Solder bath specifications, including temperature and impurities CBTL06141 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer © NXP B.V. 2010. All rights reserved ...
Page 14
... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 5. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer Figure 5) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 ...
Page 15
... PCB SMA TDR AUX HPD GPU PCIe 15. Revision history Table 17. Revision history Document ID Release date CBTL06141 v.2 20100715 • Modifications: Removed “COMPANY CONFIDENTIAL” watermark CBTL06141 v.1 20080624 CBTL06141 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature ...
Page 16
... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer © NXP B.V. 2010. All rights reserved ...
Page 17
... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2010 CBTL06141 Gen1 display multiplexer © NXP B.V. 2010. All rights reserved ...
Page 18
... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 15 July 2010 Document identifier: CBTL06141 ...