sak-c167cr-16rm ETC-unknow, sak-c167cr-16rm Datasheet - Page 47

• Manufacturer Part Number: sak-c167cr-16rm
• Description: Microcomputer Components 16-bit Cmos Single-chip Microcontrollers
• Manufacturer: ETC-unknow

Phase Locked Loop
When pin P0.15 (P0H.7) is high (‘1’) during reset the on-chip phase locked loop is enabled and
provides the CPU clock. The PLL multiplies the input frequency by 4 (ie. f
fourth transition of f
synchronization is done smoothely, ie. the CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of f
to f
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly
adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator)
the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula
and figure below).
For a period of N * TCL the minimum value is computed using the corresponding deviation D
So for a period of 3 TCLs (ie. N = 3): D
and TCL
This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial
interfaces, etc. For all slower operations and longer periods (eg. pulse train generation or
measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.
Figure 12
Approximated Maximum PLL Jitter
XTAL
4
3
2
1
Max.jitter [%]
. The slight variation causes a jitter of f
min
2
= TCL
4
TCL
NOM
XTAL
min
* (1 - 3.8 / 100) = TCL
= TCL
8
the PLL circuit synchronizes the CPU clock to the input clock. This
20Dec96@09:25h Intermediate Version
NOM
* (1 - D
3
= 4 - 3 /15 = 3.8%,
N
16
CPU
NOM
/ 100)
45
which also effects the duration of individual TCLs.
* 0.962 (24.1 nsec @ f
This approximated formula is valid for
1
CPU
D
where N = number of consecutive TCLs
and 1
N
N
= (4 - N /15) [%],
is constantly adjusted so it is locked
40 and 10MHz
N
40.
CPU
CPU
= f
Semiconductor Group
= 20 MHz).
XTAL
C167CR-16RM
f
CPU
* 4). With every
32
20MHz.
N
N
: