sak-xc161cj-16f40f Infineon Technologies Corporation, sak-xc161cj-16f40f Datasheet - Page 46

• Manufacturer Part Number: sak-xc161cj-16f40f
• Description: 16-bit Single-chip Microcontroller
• Manufacturer: Infineon Technologies Corporation

3.12
The Serial Data Link Module (SDLM) provides serial communication on a J1850 type
multiplexed serial bus via an external J1850 bus transceiver. The module conforms to
the SAE Class B J1850 specification for variable pulse width modulation (VPW).
General SDLM Features:
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Data Link Operation Features:
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Note: When the SDLM is used with the interface lines assigned to Port 4, the segment
Data Sheet
Compliant to the SAE Class B J1850 specification (VPW)
Class 2 protocol fully supported
Variable Pulse Width (VPW) operation at 10.4 kbit/s
High Speed 4X operation at 41.6 kbit/s
Programmable Normalization Bit
Programmable Delay for transceiver interface
Digital Noise Filter
Power Down mode with automatic wake-up support upon bus activity
Single Byte Header and Consolidated Header supported
CRC generation and checking
Receive and transmit Block Mode
11-Byte Transmit Buffer
Double buffered 11-Byte receive buffer (optional overwrite enable)
Support for In Frame Response (IFR) types 1, 2 and 3
Transmit and Receiver Message Buffers configurable for either FIFO or Byte mode
Advanced Interrupt Handling with 8 separately enabled sources:
– Error, format or bus shorted
– CRC error
– Lost Arbitration
– Break received
– In-Frame-Response request
– Header received
– Complete message received
– Transmit successful
Automatic IFR transmission (Types 1 and 2) for 3-Byte consolidated headers
User configurable clock divider
Bus status flags (IDLE, EOF, EOD, SOF, Tx and Rx in progress)
address output on Port 4 must be limited. CS lines can be used to increase the
total amount of addressable external memory.
Serial Data Link Module (SDLM)
44
Functional Description
XC161CJ-16F
Derivatives
V2.4, 2006-08