sak-xc888clm-8ffa Infineon Technologies Corporation, sak-xc888clm-8ffa Datasheet - Page 80
sak-xc888clm-8ffa
Manufacturer Part Number
sak-xc888clm-8ffa
Description
High Performance 8-bit Microcontroller With On-chip Flash Memory And Can
Manufacturer
Infineon Technologies Corporation
Datasheet
1.SAK-XC888CLM-8FFA.pdf
(119 pages)
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• Fractional divider (STEP/256) defined by register FDSTEP
• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
The maximum baud rate that can be generated is limited to
clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud.
Standard LIN protocal can support a maximum baud rate of 20kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20kHz to 115.2kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 29
settings and deviation errors. The fractional divider is disabled and a module clock of
24 MHz is used.
Table 29
Baud rate
19.2 kBaud
9600 Baud
4800 Baud
2400 Baud
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated.
115.2 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Data Sheet
Prelimary
baud rate
(to be considered only if fractional divider is enabled and operating in fractional divider
mode)
lists the various commonly used baud rates with their corresponding parameter
=
Table 30
---------------------------------------------------------------------------------- - where 2
16 2
Typical Baud rates for UART with Fractional Divider disabled
baud rate
×
BRPRE
lists the resulting deviation errors from generating a baud rate of
Prescaling Factor
(2
1 (BRPRE=000
1 (BRPRE=000
2 (BRPRE=001
4 (BRPRE=010
=
BRPRE
×
f
PCLK
---------------------------------------------------------------------------------- -
16 2
(
BR_VALUE
×
)
BRPRE
B
B
B
B
×
)
)
)
)
f
PCLK
+
(
76
BR_VALUE
1
)
Reload Value
(BR_VALUE + 1)
156 (9C
156 (9C
156 (9C
78 (4E
H
H
H
H
)
BRPRE
+
)
)
)
1
f
)
PCLK
×
STEP
-------------- -
×
Functional Description
/32. Hence, for a module
256
(
BR_VALUE
Deviation Error
0.17 %
0.17 %
0.17 %
0.17 %
XC886/888CLM
V0.1, 2006-02
+
1
) 1
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