w83977ctf Winbond Electronics Corp America, w83977ctf Datasheet - Page 61

• Manufacturer Part Number: w83977ctf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

TABLE 3-4 INTERRUPT CONTROL FUNCTION
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
3.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
Bit 7-4: These four bits are always logic 0.
Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt.
Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt.
Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt.
Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.
Bit
3
0
0
0
1
0
0
Bit
2
0
1
1
1
0
0
ISR
Bit
1
0
1
0
0
1
0
7
0
Bit
0
1
0
0
0
0
0
0
6
Interrupt
priority
First
Second
Second
Third
Fourth
5
-
0
4
0
Interrupt Type
UART Receive
Status
RBR Data Ready
FIFO Data Timeout
TBR Empty
Handshake status
3
2
-
1
INTERRUPT SET AND FUNCTION
0
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RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
Interrupt Source
No Interrupt pending
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
TBR empty
1. TCTS = 1
3. FERI = 1
reached
2. PBER =1
4. TDCD = 1
2. TDSR = 1
Publication Release Date: March 1999
W83977EF/ CTF
PRELIMINARY
Clear Interrupt
Read USR
1. Read RBR
2. Read RBR until FIFO
data under active level
Read RBR
1. Write data into TBR
2. Read ISR (if priority is
Read HSR
third)
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Revision A1