w83977ctf Winbond Electronics Corp America, w83977ctf Datasheet - Page 59

• Manufacturer Part Number: w83977ctf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

Bit 7: This bit is the opposite of the DCD# input. This bit is equivalent to bit 3 of HCR in loopback
Bit 6: This bit is the opposite of the RI # input. This bit is equivalent to bit 2 of HCR in loopback
Bit 5: This bit is the opposite of the DSR# input. This bit is equivalent to bit 0 of HCR in loopback
Bit 4: This bit is the opposite of the CTS# input. This bit is equivalent to bit 1 of HCR in loopback
Bit 3: TDCD. This bit indicates that the DCD# pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI # pin has changed from low to high state after HSR was
Bit 1: TDSR. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS# pin has changed state after HSR was read.
3.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
read by the CPU.
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
mode.
mode.
mode.
mode.
7
7
6
6
5
5
4
4
3
3
2
2
-50 -
1
1
0
0
Clear to send (CTS)
Data set ready (DSR)
Ring indicator (RI)
Data carrier detect (DCD)
CTS# toggling (TCTS)
RI falling edge (FERI)
DCD# toggling (TDCD)
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
DSR# toggling (TDSR)
Publication Release Date: March 1999
W83977EF/ CTF
PRELIMINARY
Revision A1