w83977atf Winbond Electronics Corp America, w83977atf Datasheet - Page 81

• Manufacturer Part Number: w83977atf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

Bit 3
Bit 2:
Bit 1:
Bit 0:
4.3 Set1 - Legacy Baud Rate Divisor Register
4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode.
Accessing these registers in Advanced IR mode will cause backward operation, that is, UART will fall
back to legacy SIR mode and clear some register values as shown in the following table.
Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any
register which is meaningful in legacy SIR/ASK-IR.
Address Offset Register Name
0
1
2
3
4
5
6
7
MIR, FIR Modes:
MIR, FIR Modes:
MIR, FIR, Remote IR Modes:
S_FEND - Set a Frame End
Set to 1 when trying to terminate the frame, that is, the procedure od PIO command is
An Entire Frame = Write Frame Data (First) + Write S_FEND (Last)
This bit should be set to 1, if used in PIO mode, to avoid transmitter underrun. Note that
setting S_FEND to 1 is equivalent to TC (Terminal Count) in DMA mode. Therefore, this
bit should be set to 0 in DMA mode.
Reserved.
LB_SF - Last Byte Stay in FIFO
A 1 in this bit indicates one or more frame ends remain in receiver FIFO.
RX_TO - Receiver FIFO or Frame Status FIFO time-out
Set to 1 when receiver FIFO or frame status FIFO time-out occurs
Set & Register
Set 0.Reg 4
Set 2.Reg 2
Set 4.Reg 3
UDR/ESCR
UCR/SSR
ISR/UFR
HCR
BHL
USR
HSR
BLL
Baud Rate Divisor Latch (Low Byte)
Baud Rate Divisor Latch (High Byte)
Interrupt Status or IR FIFO Control Register
IR Control or Sets Select Register
Handshake Control Register
IR Status Register
Handshake Status Register
User Defined Register
Advanced Mode
DIS_BACK= ¡Ñ
Bit 0, 5, 7
Bit 7~5
Bit 2, 3
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Register Description
Publication Release Date:April 1998
Legacy Mode
DIS_BACK=0
Bit 5, 7
W83977ATF
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PRELIMINARY
Revision 0.52