w83977atf Winbond Electronics Corp America, w83977atf Datasheet - Page 133

• Manufacturer Part Number: w83977atf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

CR25 (Default 0x00)
CR26 (Default 0b0s000000)
Bit 6: EN48
Bit 5 - 3: Reserved.
Bit 2: ENKBC
Bit 1: Reserved
Bit 0:
Bit 7 - 6: Reserved
Bit 5: URBTRI
Bit 4: URATRI
Bit 3: PRTTRI
Bit 2: IRTRI
Bit 1: Reserved
Bit 0: FDCTRI.
Bit 7: SEL4FDD
Bit 6: HEFRAS
Bit 5: LOCKREG
Bit 4: DSIRLGRQ
PNPCSV
= 0 The clock input on Pin 1 should be 24 Mhz.
= 1 The clock input on Pin 1 should be 48 Mhz.
The corresponding power-on setting pin is SOUTB (pin 53).
= 0 KBC is disabled after hardware reset.
= 1 KBC is enabled after hardware reset.
This bit is read only, and set/reset by power-on setting pin. The corresponding power-on
setting pin is SOUTA (pin 46).
= 0 The Compatible PnP address select registers have default values.
= 1 The Compatible PnP address select registers have no default value.
When trying to make a change to this bit, new value of
to the old one to make an effective change. For example, the user must set
first and then reset it to 1 to reset these PnP registers if the present value of
The corresponding power-on setting pin is NDTRA (pin 44).
= 0
= 1
These two bits define how to enable Configuration mode.
HEFRAS Address and Value
= 0 Write 87h to the location 3F0h twice.
= 1 Write 87h to the location 370h twice.
= 0 Enable R/W Configuration Registers.
= 1 Disable R/W Configuration Registers.
= 0 Enable IR legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
= 1 Disable IR legacy mode IRQ selecting, then MCR bit 3 is not effective on
setting pin is NRTSA (pin 43).
IRQ
selecting IRQ
Select two FDD mode.
Select four FDD mode.
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Publication Release Date: Auguest 1997
PNPCSV
The corresponding power-on
W83977ATF
must be complementary
PRELIMINARY
PNPCSV
PNPCSV
Revision 0.51
is 1.
to 0