pxb4360f Infineon Technologies Corporation, pxb4360f Datasheet - Page 21

• Manufacturer Part Number: pxb4360f
• Description: Content Addressable Memory Element Came
• Manufacturer: Infineon Technologies Corporation

The auxiliary bit VCON defines whether an entry is valid or invalid. This mechanism is used to
1)
prevent overwriting a valid connection, if the corresponding configuration bit CEE
in the
1)
TESTMODE register is set. A second configuration bit, CLE
of the TESTMODE register, is
available to prevent a multimatch entry. If CLE and CEE are set, the CAME checks whether the
PN, VPI, and VCI already exist. For the case that an entry exists (single or multimatch), the
CAME prevents the writing and outputs a failure report to the Status Register. For the case that
no entry exists (mismatch), the CAME writes the entry into memory if the LCI entry is invalid;
otherwise, the writing is also prevented. If CEE and CLE are not set, there is no checking
whether both a valid connection is changed and a multimatch condition is generated. The CEE
and CLE have an influence on the execution time of Request Command number 4.
The auxiliary bit P_IP defines whether the connection point is a Path Intermediate Point. If the
P_IP is set, the VCI values are ignored during the search process.
In the TESTMODE register, the TWE bit is provided for testing the memory. If it is set, the write
request is converted into a test write request and all memory banks are written simultaneously.
Request Command number 5 should be used to check the Search Pattern PN, VPI, and VCI and
the Search result pattern VCON and P_IP for a given LCI. First, the LCI (14 bits) is written into
the Address Register, via the Data bus. Then the PN, VPI, VCI, VCON, and P_IP are written
from memory to the Read Data Register. The Read Data Register and the Status Register are
read out via the data bus of the CAME.
In the TESTMODE register, the TRE bit is provided for testing the memory. If it is set, the read
request is converted into a test read request and all memory banks are read simultaneously.
Request Command number 3 should be used to search for a Search Pattern with deactivated
search fields, as defined in the TESTMODE register. This Request Command should be
activated by the microprocessor via the ALP and the CAME Interface. It is not used during
normal cell processing. First, the PN, VPI, and VCI are written into the Search Address Register,
via the Data bus. After a predefined search period, the search results (LCI and the two auxiliary
bits VCON and P_IP) are written into the Search Data Register. The status information in the
Status Register and the contents of the Search Data Register are read out via the Data bus of
the CAME.
In the TESTMODE register, the bits VCEN, VPEN, and VSET are provided to define whether the
VCI or the PN and VPI are ignored. Furthermore, it is possible to search for invalid and free
entries, identified by VCON as equal to zero. Additionally, a TSE bit is implemented to convert
the search request into a test search request which compares all memory banks in parallel.
Request Command number 6 is implemented to configure the CAME for operation and test. This
request is a substitute for the microprocessor interface. The configuration and test mode
commands are written into the TESTMODE register via the Data bus of the CAME. Herewith it
is possible to:
• Check the cascade interface between the Master and Slave CAME devices
• Check the parity of the Data bus and Address bus of the CAME
• Read the version number of the CAME
1)
Note that CEE and CLE are not supported by the ALP
Data Sheet
4-21
07.2000