ncn6001 ON Semiconductor, ncn6001 Datasheet - Page 20

• Manufacturer Part Number: ncn6001
• Description: Compact Smart Card Interface Ic
• Manufacturer: ON Semiconductor

the internal shift register is latched on the positive going
have an individual physical address, the system can control
several of these chips by sending the data content within the
same CS frame as depicted in Figure 13. The bits are
decoded on the fly and the related sub blocks are updated
accordingly. According to the SPI general specification, no
code or activity will be transferred to any chip when the CS
is High.
Special Mode
Normal Mode
When the eight bits transfer is completed, the content of
Since the four chips present in the Asynchronous Bank
ADDRESS
SET_VCC
SET_RST
SET_CLK
DECODE
SPI_CLK
MOSI
MISO
MISO
CS
MPU Enables
Clock
MISO Line = High Impedance
MISO Line = High Impedance
MSB
B7
ADDRESS
CHIP
Figure 14. Programming Sequence, Chip Address = $03
B6
B5
Figure 13. Basic Multi Command SPI Bytes
Chip Nx
B4
Normal Mode: MISO is synchronized with
the SPI_CLK Negative going slope
AND CONTROL
COMMAND
B3
Select Chip from SYNCHRONOUS Bank
http://onsemi.com
B2
NCN6001
B1
20
B0
edge of the CS signal and the NCN6001 related functions are
updated accordingly.
MOSI line, the CLK_SPI sequence must be separated by at
least one half positive period of this clock (see td
parameter).
illustrate the SPI communication protocol (source:
NCN6001 demo board).
LSB
When two SPI bytes are sequentially transferred on the
The oscillograms shown in Figure 14 and Figure 15
tdclk
MSB
B7
B6
B5
B4
Chip Ny
Special Mode: MISO
is synchronized with
the SPI_CLK Positive
going slope
B3
B2
B1
B0
LSB
clk