ncn6001 ON Semiconductor, ncn6001 Datasheet - Page 18

• Manufacturer Part Number: ncn6001
• Description: Compact Smart Card Interface Ic
• Manufacturer: ON Semiconductor

Table 7. Interrupt Reset Logic
INTERRUPT
upon POR signal. The interrupt pin 2 is forced LOW when
either a card is inserted/extracted, or when a fault is
developed across the CRD_VCC output voltage. This signal
Card Insertion
Card Insertion
Over Load
identify the source of the interrupt.
Table 8. Interrupt Reset Logic Operation
CRD_VCC > 0 V
CRD_VCC = 0 V
When the system is powered up, the INT pin is set to High
When several interfaces share the same digital mC bus, it is up to the software to pool the chips, using the MISO register to
Interrupt Source
MOSI_b0
MOSI_b1
T10
T11
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
OVER LOAD
CRD_VCC
CRD_DET
A card has been inserted into the reader and detected by the CRD_DET signal. The NCN6001 pulls down the interrupt line.
The mC sets the CS signal to Low, the chip is now active, assuming the right address has been placed by the MOSI register.
The mC acknowledges the interrupt and resets the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
The card has been extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L). On the other hand, the
PWR_DOWN sequence is activated by the NCN6001.
The interrupt pin is clear by the zero volt programmed to the interface.
Same as T0
The mC start the DC/DC converter, the interrupt is cleared (same as T2)
An overload has been detected by the chip : the CRD_VCC voltage is zero, the INT goes Low.
The card is extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L).
The card is re−inserted before the interrupt is acknowledged by the mC: the INT pin stays Low.
The mC acknowledges the interrupt and reset the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
The Chip Select signal goes High, all the related NCN6001 interface(s) are deactivated and no further programming or
transaction can take place.
INT
CS
1
2
T0
3
CS
L
L
L
T1
CRD_VCC
> 0
= 0
= 0
T2
Figure 10. Basic Interrupt Function
http://onsemi.com
Selected Chip MOSI[b7 : B5] = 0xx or MOSI[b7 : B5] = 101
Selected Chip MOSI[b7 :B5] = 0xx or MOSI[b7 : B5] = 101
Selected Chip MOSI[b7 : B5] = 0xx or MOSI[b7 : B5] = 101
T3
NCN6001
18
T4
is neither combined with the CS signal, nor with the chip
address. Consequently, an interrupt is placed on the mC input
as soon as one of the condition is met.
given in Table 7.
The INT signal is clear to High upon one of the condition
T5
T6
Chip Address
T7
T8
T9
T10
T11