hctl-2016-plc Avago Technologies, hctl-2016-plc Datasheet - Page 4

• Manufacturer Part Number: hctl-2016-plc
• Description: Quadrature Decoder/counter Interface Ics
• Manufacturer: Avago Technologies

4
Functional Pin Description
Table 4. Functional Pin Descriptions
CNT
Symbol 2000/2016 2020
CNT
CHA
CHB
CLK
RST
SEL
U/D
V
OE
NC
V
D0
D1
D2
D3
D4
D5
D6
D7
DD
SS
DCDR
CAS
Pin
16
15
14
13
12
11
10
8
2
7
6
5
4
3
1
9
Pin
10
16
15
19
18
17
14
13
12
11
20
2
9
8
7
4
3
5
1
6
These LSTTL-compatible tri-state outputs form an 8-bit output port
through which the contents of the 12/16-bit position latch may be read in
2 sequential bytes. The high byte, containing bits 8-15, is read first (on the
HCTL-2000, the most significant 4 bits of this byte are set to 0 internally).
The lower byte, bits 0-7, is read second.
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA and CHB are Schmitt-trigger inputs which accept the outputs
from a quadrature encoded source, such as incremental optical shaft
encoder. Two channels, A and B, nominally 90 degrees out of phase,
are required.
This active low Schmitt-trigger input clears the internal position
counter and the position latch. It also resets the inhibit logic. RST is
asynchronous with respect to any other input signals.
This CMOS active low input enables the tri-state output buffers. The
OE and SEL inputs are sampled by the internal inhibit logic on the
falling edge of the clock to control the loading of the internal position
data latch.
This CMOS input directly controls which data byte from the position
latch is enabled into the 8-bit tri-state output buffer. As in OE above,
SEL also controls the internal inhibit logic.
A pulse is presented on this LSTTL-compatible output when the
quadrature decoder has detected a state transition.
This LSTTL-compatible output allows the user to determine whether
the IC is counting up or down and is intended to be used with the
CNT
(low level) will be present before the rising edge of the CNT
CNT
A pulse is presented on this LSTTL-compatible output when the
HCTL-2020 internal counter overflows or underflows. The rising edge
on this waveform may be used to trigger an external counter.
Not connected - this pin should be left floating.
DCDR
CAS
outputs.
and CNT
SEL
0
1
CAS
outputs. The proper signal U (high level) or D
BYTE SELECTED
Description
High
Low
DCDR
and