hctl-2016-plc Avago Technologies, hctl-2016-plc Datasheet - Page 17

• Manufacturer Part Number: hctl-2016-plc
• Description: Quadrature Decoder/counter Interface Ics
• Manufacturer: Avago Technologies

Interfacing the HCTL-20XX to an
Intel 8748
The circuit shown in Figure 17
shows the connections between
an HCTL-20XX and an 8748.
Data lines D0-D7 are connected
to the 8748 bus port. Bits 0 and 1
of port 1 are used to control the
OE and SEL inputs of the HCTL-
20XX respectively. T0 is used to
provide a clock signal to the
HCTL-20XX. The frequency of T0
* NOTE: PIN NUMBERS ARE DIFFERENT FOR THE HCTL-2020.
Figure 17. An HCTL-20XX-to-Intel 8748 Interface.
17
Figure 18. A Typical Program for Reading HCTL-20XX with an 8748.
LOC
00B
000
002
003
004
006
008
009
Object
Code
99 00
A8
89 02
A9
89 03
08
08
93
MOVE R0, A
ANL P1, 00H
ORL P1, 02H
ORL P1, 03H
RETR
INS A, BUS
INS A, BUS
MOV R1, A
Statements
Source
Enable output and higher order
bits
Load higher order bits into ACC
Move data to register 0
Enable output and lower order
bits
Load order bits into AC
Move data to register 1
Disable outputs
Return
is the crystal frequency divided
by 3. T0 must be enabled by
executing the ENT0 CLK
instruction after each system
reset, but prior to the first
encoder position change. An
8748 program which interfaces
to the circuit in Figure 17 is
given in Figure 18. The resulting
interface timing is shown in
Figure 19.
Comments