sclt3-8bt8-tr STMicroelectronics, sclt3-8bt8-tr Datasheet - Page 5

• Manufacturer Part Number: sclt3-8bt8-tr
• Description: Protected Digital Input Termination With Serialized State Transfer
• Manufacturer: STMicroelectronics

SCLT3-8BT8
1.1
I/O pin descriptions
Table 1.
Figure 2.
COM
COM
/MISO
Name
MOSI
MISO
OSC
SPM
REF
DVR
SCK
SUB
V
V
/CS
LD
NC
IN
V
CS
DD
C
I
I
P
S
Power input
Power output
Power input
Signal input
Ground
Power output 5 V logic power supply
Ground
Signal input
Logic input
Signal input
Signal input
Logic input
Logic input
Logic output
Logic output
Logic input
Substrate
I/O pin descriptions
Pinout description of the HTSSOP-38 version (top view)
Type
Logic input with a current regulation behavior, I = 1 to 8
LED output driver with a current regulation behavior,
I = 1 to 8
24 V sensor power supply
24 V sensor power supply sensing input
Power ground of power sensor supply
Signal ground of logic / output section
Input current limiter reference setting
Divider ratio selector of the digital input filters (8 or 64 steps)
Delay setting of the digital input filters
SPI shift register length selector (8 or 16 bits)
SPI chip Select signal
SPI serial clock signal
SPI serial data input signal
Inverting SPI serial data output signal
SPI serial data input signal
Exposed pad: connected to die substrate, to connect to
COMP
Not connected (or to be connected to COM
P
Doc ID 15191 Rev 3
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
17
17
17
17
18
18
18
18
19
19
19
19
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
DVR
DVR
DVR
OSC
OSC
OSC
SPM
SPM
SPM
COM
COM
COM
V
V
V
V
V
V
COM
COM
COM
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
COM
COM
COM
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
COM
COM
COM
NC
NC
NC
NC
NC
NC
C
C
C
CS
CS
CS
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
SCLT3 -8BT8
SCLT3 -8BT8
P
P
P
P
P
P
P
P
P
P
P
P
SUB
SUB
SUB
SUB
SUB
SUB
Description
/MISO
/MISO
/MISO
COM
COM
COM
MOSI
MOSI
MOSI
MISO
MISO
MISO
SCK
SCK
SCK
REF
REF
REF
/CS
/CS
/CS
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
V
V
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
DD
DD
DD
S
S
S
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
6
6
6
7
7
7
8
8
8
38
38
38
38
37
37
37
37
36
36
36
36
35
35
35
35
34
34
34
34
33
33
33
33
32
32
32
32
31
31
31
31
30
30
30
30
29
29
29
29
28
28
28
28
27
27
27
27
26
26
26
26
25
25
25
25
24
24
24
24
23
23
23
23
22
22
22
22
21
21
21
21
20
20
20
20
P
)
Circuit block diagram
4, 7, 12, 17
8 to 11, 13
18, 19, 28,
Exposed
20 to 27
36, 37
Pin #
to 16
pad
38
29
35
34
33
32
31
30
5
6
1
2
3
5/33