lm2502sm National Semiconductor Corporation, lm2502sm Datasheet - Page 25

• Manufacturer Part Number: lm2502sm
• Description: Mobile Pixel Link Mpl Display Interface Serializer And Deserializer
• Manufacturer: National Semiconductor Corporation

Application Information
Figure 21 shows the typical timing of the RGB application.
The 6X PLL setting (PLLCON[2:0] = 010’b) is selected. The
PCLK is applied to both the WR* and CLK inputs on the
Master. The rising edge on the WR* (PCLK) signal samples
the data by the Master for serialization. The CLK input can
be the PCLK (if timing requirements are met) or a synchro-
nous clock to the PCLK signal. The HS connects to the CS1*
signal and the HS* (inverted HS) is connected to the CS2*.
(Continued)
FIGURE 21. RGB565 Application Timing
25
With this configuration there will always be a valid CS* LOW
on the Master input. The RGB information is then serialized
and passed to the Slave via the MPL bus. It takes 5 MC
cycles to complete the transfer and with the 6X PLL setting,
there will be two idle bits on the MD (1 MC cycle) lines before
the next transfer. Recovery of the RGB interface (RGB565,
HS, VS and PCLK) is provided at the Slave output. The
PCLK is slightly shifted later in time (1 MC cycle) but ad-
equate timing margin (increased set, shorted hold) is still
provided.
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