lm2502sm National Semiconductor Corporation, lm2502sm Datasheet - Page 10

• Manufacturer Part Number: lm2502sm
• Description: Mobile Pixel Link Mpl Display Interface Serializer And Deserializer
• Manufacturer: National Semiconductor Corporation

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OFF (O)
IDLE (I)
Active (A)
LINK-UP
(LU)
Functional Description
SERIAL BUS PHASES
There are four bus phases on the MPL serial bus. These are
determined by the state of the MC and MD lines. The MPL
bus phases are shown in Table 3 .
Notes on MC/MD Line State:
0 = no current (off)
L = Logic Low — The higher level of current on the MC and MD lines
H = Logic High — The lower level of current on the MC and MD lines
X = Low or High
A = Active Clock
SERIAL BUS START UP TIMING
In the Serial Bus OFF phase, Master transmitters for MD0,
MD1 and MC are turned off such that zero current flows over
the MPL lines. In addition, both the Master and the Slave are
internally held in a low power state. When the PD* input pins
are de-asserted (driven High) the Master enables its PLL
and waits for enough time to pass for its PLL to lock. After the
Master’s PLL is locked (t0 = 4,096 CLK Cycles), the Master
will perform an MPL start up sequence. The Slave will also
power up and await the start up sequence from the Master.
The MPL start up sequence gives the Slave an opportunity to
optimize the current sources in its transceiver to maximize
noise margins. The Master begins the sequence by driving
the MC line logically Low for 11 CLK cycles (t1). During this
part of the sequence the Slave’s transceiver samples the MC
current flow and adjusts itself to interpret that amount of
current as a logical Low. Next the Master drives the MC line
logically HIGH for 11 CLK cycles (t2). On the Low-to-High
Name
Data Out
WRITE
Data In
READ
Master
MC State
A
A
A
H
0
(Continued)
MDn State
X
X
0
L
-
TABLE 3. Link Phases
Link is Off
Data is Static (Low)
Data Out (Write) — includes
command, Data Out Phases
Data In (Read) — includes
command, TA’, Data In, and TA”
phases
Master initiated Link-Up
10
Phase Description
transition of the MC – point B – the Slave latches the current
source configuration. This optimized configuration is held as
long as the MPL remains up. Next, the Master drives both
the MC and the MD lines to a logical Low for another 11 CLK
cycles (t3), after which it begins to toggle the MC line at a
rate determined by its PLL Configuration pins. The Master
will continue to toggle the MC line as long as its PD* pin
remains de-asserted (High). At this point the MPL bus may
remain in IDLE phase, enter the ACTIVE phase or return to
the OFF phase. Active data will occur at the Slave output
latency delays (Master + line + Slave) after the data is
applied to the Master input. Possible start points are shown
by the “C” arrow in Figure 6 .
After seven subsequent MC cycles the Slave will start tog-
gling its CLK pin at a rate configured by its CLK Divisor pins.
In the Figure 6 example, an IDLE bus phase is shown until
point C, after which the bus is active and the High start bit on
MD initiates the transfer of information.
Pre-Phase
LU, A, or I
LU, A, or I
A, I or LU
A or LU
O
Post-Phase
A, I, or O
A, I, or O
A, I, or O
A or O
LU