sx8724s Semtech Corporation, sx8724s Datasheet - Page 40

• Manufacturer Part Number: sx8724s
• Description: Zoomingadc For Sensing Data Acquisition
• Manufacturer: Semtech Corporation

Revision 1.0
© Semtech
the master in this mode if to be synchronized to the ADC end of conversion. The DataReadyEn bit modifies only the
MISO/READY pin functionality. The READY pin functionality remains unaffected. In either mode, the MISO/READY pin
goes to a high-impedance state when SS is taken high.
When the DataReadyEn bit in RegACCfg4[0x56] register is set to '1', this pin functions as both MISO and READY. Data
are shifted out from this pin, MSB first, at the falling edge of SCLK. When the DataReadyModeEn bit is enabled and a
new conversion is complete, MISO/READY goes low if it is high. If it is already low, then MISO/READY goes high and then
goes low (see
Similar to the READY pin (but with opposite polarity), a falling edge on the MISO/READY pin signals that a new
conversion result is ready. After MISO/READY goes low, the data can be clocked out by providing 16 clocks pulses on
SCLK.
In order to force MISO/READY high (so that MISO/READY can be polled for a '0' instead of waiting for a falling edge), a no
operation command (NOP) or any other command that does not load the data output register can be sent after
ADVANCED COMMUNICATIONS & SENSING
Figure 27
SCLK
SS
MOSI
MISO/
READY
READY
February 2011
Figure 27. Data Retrieval with the COMBINED DATA READY mode enabled
below).
ADC end of conversion, sample READY
MASTER
D15
MISO/READY
1
D14
ADC sample MSB shifted out
2
SCLK
MOSI
D13
(RegACOutMsb)
SS
3
Figure 26. Example of 4-wire Slave
D12
4
D11
5
D10
Page 40
6
D9
7
D8
8
NOP
D7
ZoomingADC for sensing data acquisition
9
D6
ADC sample LSB shifted out
10
D5
SCLK
MOSI
MISO/READY
SS
11
(RegACOutLsb)
D4
12
D3
13
SX872xS
SLAVE
D2
14
D1
15
SX8724S
D0
16
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