sx8724s Semtech Corporation, sx8724s Datasheet - Page 20

• Manufacturer Part Number: sx8724s
• Description: Zoomingadc For Sensing Data Acquisition
• Manufacturer: Semtech Corporation

Revision 1.0
© Semtech
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7.3 Input Multiplexers (AMUX and VMUX)
The ZoomingADC has analog inputs AC0 to AC7 and reference inputs. Let us first define the differential input voltage
V
ADVANCED COMMUNICATIONS & SENSING
IN
and reference voltage V
SetNelconv: (rw) sets the number of elementary conversions to 2
between elementary conversions (1,2,4,8).
SetOsr: (rw) sets the over-sampling rate (OSR) of an elementary conversion to 2
Continuous: (rw) setting this bit starts a conversion. When this bis is 1, A new conversion will automatically begin directly when the previ-
ous one is finished.
SampleShiftEn: (rw) the 16-bit samples can be directly shifted out though the SPI interface by the master when a conversion is done.
IbAmpAdc: (rw) sets the bias current in the ADC to 0.25 x (1+ IbAmpAdc[1:0]) of the normal operation current (25, 50, 75 or 100% of nom-
inal current). To be used for low-power, low-speed operation.
IbAmpPga: (rw) sets the bias current in the PGAs to 0.25 x (1+IbAmpPga[1:0]) of the normal operation current (25, 50, 75 or 100% of nom-
inal current). To be used for low-power, low-speed operation.
Enable: (rw) enables the ADC modulator (bit 0) and the different stages of the PGAs (PGAi by bit i=1,2,3). PGA stages that are disabled are
bypassed.
SetFs: (rw) These bits set the over sampling frequency of the acquisition chain. Expressed as a fraction of the oscillator frequency, the
sampling frequency is given as: 11 ' 500 kHz, 10 ' 250 kHz, 01 ' 125 kHz, 00 ' 62.5 kHz.
Pga1Gain: (rw) sets the gain of the first stage: 0 ' 1, 1 ' 10.
Pga2Gain: (rw) sets the gain of the second stage: 00 ' 1, 01 ' 2, 10 ' 5, 11 ' 10.
Pga3Gain: (rw) sets the gain of the third stage to Pga3Gain[6:0] 1/12.
Pga2Offset: (rw) sets the offset of the second stage between -1 and +1, with increments of 0.2. The MSB gives the sign (0 positive, 1 neg-
ative); amplitude is coded with the bits Pga2Offset[5:0].
DataReadyEn: (rw) enables the combined data ready mode with the MISO of the SPI interface.
Pga3Offset: (rw) sets the offset of the third stage between -5.25 and +5.25, with increments of 1/12. The MSB gives the sign (0 positive, 1
negative); amplitude is coded with the bits Pga3Offset[5:0].
Busy: (r) set to 1 if a conversion is running.
Def: (w) sets all values to their defaults (PGA disabled, AMux not changed, VMux not changed, ADC enabled, nominal modulator bias cur-
rent (100%), 2 elementary conversions, OSR = 32, N
preceding one.
Amux(4:0): (rw) Amux[4] sets the mode (0 ' differential inputs, 1 ' single ended inputs with A0= common reference) Amux[3] sets the sign
(0 ' straight, 1' cross) Amux[2:0] sets the channel.
Vmux: (rw) sets the differential reference channel (0 ' V
February 2011
REF,ADC
respectively as:
V
REF
V
ELCONV
IN
=
BATT
=
V
Page 20
Equation 3
Equation 4
V
,
= 2, fs = 62.5kHz) and starts a new conversion without waiting the end of the
REFP
1 ' V
INP
REF
−
−
V
V
).
(SetNelconv[1:0])
INN
REFN
ZoomingADC for sensing data acquisition
[V
[V
]
(3+SetOsr[2:0])
]
. To compensate for offsets, the input signal is chopped
. OSR = 8, 16, 32, ..., 512, 1024.
SX8724S
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