sx8724s Semtech Corporation, sx8724s Datasheet - Page 35

• Manufacturer Part Number: sx8724s
• Description: Zoomingadc For Sensing Data Acquisition
• Manufacturer: Semtech Corporation

Revision 1.0
© Semtech
9 SPI interface
9.1 Overview
The SX8724S serial port interface implements the following:
The serial interface is a slave port for communication with a serial microprocessor bus, allowing the SX8724S to be
controlled by an external processor. The serial interface header must be connected to the host processor, which acts as
the master.
The serial interface signals are:
The address and data are transmitted and received MSB first. Valid read/write accesses are possible only when SS is
active. MISO and MOSI lines are push-pull pads. As the waveforms illustrate (see below), the slave interface implements
a 16-bit shift register. The SPI implemented on the SX8724S is set to the common setting CPOL=0 and CPHA=0 which
means data are sampled on the rising edge of the clock, and shifted on the falling one.
The first bit in the serial data is the Direction Bit. This must be set to '1' for reading, and '0' for writing. The following 7
bits represent the target register address, shifted in MSB first. The next byte represents register data, shifted in/out MSB
first.
ADVANCED COMMUNICATIONS & SENSING
4-pin Interface + options for synchronization to ADC sample ready
7-bit Target Address (max 128 registers)
2 Mbps serial clock
MSB first
SCLK:
SS:
MISO/READY:
MOSI:
Serial Clock
Active low Slave Select
Master Input, Slave Output (data out) and optional active low ADC data Ready signal.
Master Output, Slave Input.
February 2011
MASTER
Figure 18. Example of SPI bus with 1 master and 3 slaves
MOSI
MISO
SCLK
SS1
SS2
SS3
Page 35
ZoomingADC for sensing data acquisition
SCLK
MOSI
MISO
SS
SCLK
MOSI
MISO
SS
SCLK
MOSI
MISO
SS
SLAVE 1
SLAVE 2
SLAVE 3
SX8724S
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