tda5235 Infineon Technologies Corporation, tda5235 Datasheet - Page 92

• Manufacturer Part Number: tda5235
• Description: Enhanced Sensitivity Double-configuration Receiver With Digital Baseband Processing
• Manufacturer: Infineon Technologies Corporation

The SPI also includes a safety feature by which the checksum is calculated with an
XOR operation from the address and the data when writing SFR registers. The
checksum is in fact an XOR of the data 8-bitwise after every 8 bits of the SPI write
command. The calculated checksum value is automatically written in the SPICHKSUM
register and can be compared with the expected value. After the SPICHKSUM register
is read, its value is cleared.
In case of an SPI Burst Write frame, a checksum is calculated from the SPI start address
and consecutive data fields.
Figure 63
To read the FIFO, the SPI master has to select the SPI slave unit first. Therefore, the
master must set the NCS line to low. After this, the instruction byte is shifted in on SDI
and stored in the internal instruction register. The data bits of the FIFO are then shifted
out on SDO. The following byte is a status word that contains the number of valid bits in
the data packet. After completing the read operation, the master sets the NCS line to
high.
Figure 64
Table 4
Data Sheet
NCS
SCK
SDO
SDI
Instruction
WR
RD
RDF
WRB
RDB
high impedance Z
I7
1
I6
Instruction
Read FIFO
Instruction Set
SPI Checksum Generation
I1
I0
8
D0
1
D1
SPI shift register
32 FIFO Bits
Frame
Description
Write to chip
Read from chip
Read FIFO from chip
Write to chip in Burst mode
Read from chip in Burst mode 0000 0101
D30
D31
32
S7
1
S6
Status Word
S1
S0
8
XOR
92
I7
1
I6
Instruction
Checksum SFR
I1
I0
8
D0
Instruction Format
0000 0010
0000 0011
0000 0100
0000 0001
1
D1
32 FIFO Bits
Frame
enable every 8 bit
D30
D31
Functional Description
32
S7
read/clear
1
S6
Status Word
V1.0, 2010-02-19
S1
S0
8
TDA5235