tda5235 Infineon Technologies Corporation, tda5235 Datasheet - Page 41
tda5235
Manufacturer Part Number
tda5235
Description
Enhanced Sensitivity Double-configuration Receiver With Digital Baseband Processing
Manufacturer
Infineon Technologies Corporation
Datasheet
1.TDA5235.pdf
(259 pages)
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Part Number:
TDA5235
Manufacturer:
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TDA5235
Functional Description
hexadecimals. For a final application the Signal Detector Threshold should be varied to
optimize the false alarm rate and the sensitivity.
Verification if Squelch only is possible
Apply a bit pattern (e.g. PRBS9) with correct data rate at about -80 dBm input signal
power and minimum FSK deviation to the RF input. Do 500 (50) readings of SPWR,
calculate average minus three times the Standard Deviation. This value should be higher
than the calculated Signal Detector Threshold calculated above. If this is not the case,
Signal Detector AND Noise Detector must be used.
Noise Detector Threshold
Do 500 (50) readings of NPWR with no RF input signal applied (=noise only). Calculate
average and Standard Deviation. Noise Detector Threshold is average minus the
Standard Deviation. Round this value and convert it to hexadecimals. For a final
application, the Noise Detector Threshold should be varied to optimize false alarm rate
and sensitivity.
Signal Detector Low Threshold
The Signal Detector Low Threshold is always required in combination with the Noise
Detector.
Set register bit SDLORE to 1 and set bit group SDLORSEL to 00. Apply a bit pattern (e.g.
PRBS9) at correct data rate at about -80 dBm input signal power and minimum FSK
deviation to the RF input. Do 500 (50) readings of SPWR, calculate average. If average
is larger than 200 dec (=0xC8), SDLORSEL has to be increased to the next larger value
until average is smaller than 200 dec. x_SIGDETLO = 0.8 * (average - 3 * Standard
Deviation). Set register SDLORE back to 0. The last setting of bit group SDLORSEL
must also be used for configuration!
Verification
Threshold settings should be verified by testing receiver sensitivity over the input
frequency range, with a step size of 100Hz, at minimum FSK deviation with all
combinations of minimum and maximum data rate and duty cycle.
Further detailed information can be taken from the corresponding Application Note.
Data Sheet
41
V1.0, 2010-02-19
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