tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 120

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

Table 2
Register Short Name
C_PLLFRAC2C2
C_PLLINTC3
C_PLLFRAC0C3
C_PLLFRAC1C3
C_PLLFRAC2C3
D_IF1
D_WURSSITH1
D_WURSSIBL1
D_WURSSIBH1
D_WURSSITH2
D_WURSSIBL2
D_WURSSIBH2
D_WURSSITH3
D_WURSSIBL3
D_WURSSIBH3
D_WULOT
D_AFCLIMIT
D_AFCAGCD
D_AFCSFCFG
D_AFCK1CFG0
D_AFCK1CFG1
D_AFCK2CFG0
D_AFCK2CFG1
D_PMFUDSF
D_AGCSFCFG
D_AGCCFG0
D_AGCCFG1
D_AGCTHR
D_DIGRXC
D_ISUPFCSEL
D_PDECF
D_PDECSCFSK
D_PDECSCASK
D_MFC
Data Sheet
Register Overview and Reset Value (cont’d)
Register Long Name
PLL Fractional Division Ratio Register 2 Channel 2 260
PLL MMD Integer Value Register Channel 3
PLL Fractional Division Ratio Register 0 Channel 3 262
PLL Fractional Division Ratio Register 1 Channel 3 263
PLL Fractional Division Ratio Register 2 Channel 3 264
RSSI Wake-Up Threshold for Channel 1 Register 31B
RSSI Wake-Up Blocking Level Low Channel 1
Register
RSSI Wake-Up Blocking Level High Channel 1
Register
RSSI Wake-Up Threshold for Channel 2 Register 31E
RSSI Wake-Up Blocking Level Low Channel 2
Register
RSSI Wake-Up Blocking Level High Channel 2
Register
RSSI Wake-Up Threshold for Channel 3 Register 321
RSSI Wake-Up Blocking Level Low Channel 3
Register
RSSI Wake-Up Blocking Level High Channel 3
Register
Wake-Up on Level Observation Time Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
AGC Configuration Register 1
AGC Threshold Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
IF1 Register
Digital Receiver Configuration Register
120
Offset Address
261
316
31C
31D
31F
320
322
323
325
32A
32B
32C
32D
32E
32F
330
331
332
333
334
335
336
338
339
33A
33B
33C
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Overview
V1.0, 2010-02-19
Reset Value
09
13
F3
07
09
20
00
FF
00
00
FF
00
00
FF
00
00
02
00
00
00
00
00
00
42
00
2B
03
08
40
07
00
00
20
07
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Appendix
TDA5225