tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 119

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

Table 2
Register Short Name
C_WURSSITH2
C_WURSSIBL2
C_WURSSIBH2
C_WURSSITH3
C_WURSSIBL3
C_WURSSIBH3
C_WULOT
C_AFCLIMIT
C_AFCAGCD
C_AFCSFCFG
C_AFCK1CFG0
C_AFCK1CFG1
C_AFCK2CFG0
C_AFCK2CFG1
C_PMFUDSF
C_AGCSFCFG
C_AGCCFG0
C_AGCCFG1
C_AGCTHR
C_DIGRXC
C_ISUPFCSEL
C_PDECF
C_PDECSCFSK
C_PDECSCASK
C_MFC
C_SRC
C_EXTSLC
C_CHCFG
C_PLLINTC1
C_PLLFRAC0C1
C_PLLFRAC1C1
C_PLLFRAC2C1
C_PLLINTC2
C_PLLFRAC0C2
C_PLLFRAC1C2
Data Sheet
Register Overview and Reset Value (cont’d)
Register Long Name
RSSI Wake-Up Threshold for Channel 2 Register 21E
RSSI Wake-Up Blocking Level Low Channel 2
Register
RSSI Wake-Up Blocking Level High Channel 2
Register
RSSI Wake-Up Threshold for Channel 3 Register 221
RSSI Wake-Up Blocking Level Low Channel 3
Register
RSSI Wake-Up Blocking Level High Channel 3
Register
Wake-Up on Level Observation Time Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
AGC Configuration Register 1
AGC Threshold Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
PLL MMD Integer Value Register Channel 1
PLL Fractional Division Ratio Register 0 Channel 1 25A
PLL Fractional Division Ratio Register 1 Channel 1 25B
PLL Fractional Division Ratio Register 2 Channel 1 25C
PLL MMD Integer Value Register Channel 2
PLL Fractional Division Ratio Register 0 Channel 2 25E
PLL Fractional Division Ratio Register 1 Channel 2 25F
Digital Receiver Configuration Register
Channel Configuration Register
119
Offset Address
21F
220
222
223
225
22A
22B
22C
22D
22E
22F
230
231
232
233
234
235
236
238
239
23A
23B
23C
23D
23E
258
259
25D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Overview
V1.0, 2010-02-19
Reset Value
00
FF
00
00
FF
00
00
02
00
00
00
00
00
00
42
00
2B
03
08
40
07
00
00
20
07
00
02
44
93
F3
07
09
13
F3
07
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Appendix
TDA5225