tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 118

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

Table 2
Register Short Name
B_AFCLIMIT
B_AFCAGCD
B_AFCSFCFG
B_AFCK1CFG0
B_AFCK1CFG1
B_AFCK2CFG0
B_AFCK2CFG1
B_PMFUDSF
B_AGCSFCFG
B_AGCCFG0
B_AGCCFG1
B_AGCTHR
B_DIGRXC
B_ISUPFCSEL
B_PDECF
B_PDECSCFSK
B_PDECSCASK
B_MFC
B_SRC
B_EXTSLC
B_CHCFG
B_PLLINTC1
B_PLLFRAC0C1
B_PLLFRAC1C1
B_PLLFRAC2C1
B_PLLINTC2
B_PLLFRAC0C2
B_PLLFRAC1C2
B_PLLFRAC2C2
B_PLLINTC3
B_PLLFRAC0C3
B_PLLFRAC1C3
B_PLLFRAC2C3
C_IF1
C_WURSSITH1
C_WURSSIBL1
C_WURSSIBH1
Data Sheet
Register Overview and Reset Value (cont’d)
Register Long Name
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
AGC Configuration Register 1
AGC Threshold Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
Pre Decimation Scaling Register FSK Mode
Pre Decimation Scaling Register ASK Mode
Matched Filter Control Register
Sampe Rate Converter NCO Tune
Externel Data Slicer Configuration
PLL MMD Integer Value Register Channel 1
PLL Fractional Division Ratio Register 0 Channel 1 15A
PLL Fractional Division Ratio Register 1 Channel 1 15B
PLL Fractional Division Ratio Register 2 Channel 1 15C
PLL MMD Integer Value Register Channel 2
PLL Fractional Division Ratio Register 0 Channel 2 15E
PLL Fractional Division Ratio Register 1 Channel 2 15F
PLL Fractional Division Ratio Register 2 Channel 2 160
PLL MMD Integer Value Register Channel 3
PLL Fractional Division Ratio Register 0 Channel 3 162
PLL Fractional Division Ratio Register 1 Channel 3 163
PLL Fractional Division Ratio Register 2 Channel 3 164
RSSI Wake-Up Threshold for Channel 1 Register 21B
RSSI Wake-Up Blocking Level Low Channel 1
Register
RSSI Wake-Up Blocking Level High Channel 1
Register
Digital Receiver Configuration Register
Channel Configuration Register
IF1 Register
118
Offset Address
12A
12B
12C
12D
12E
12F
130
131
132
133
134
135
136
138
139
13A
13B
13C
13D
13E
158
159
15D
161
216
21C
21D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Overview
V1.0, 2010-02-19
Reset Value
02
00
00
00
00
00
00
42
00
2B
03
08
40
07
00
00
20
07
00
02
44
93
F3
07
09
13
F3
07
09
13
F3
07
09
20
00
FF
00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Appendix
TDA5225