qf4a512 ETC-unknow, qf4a512 Datasheet - Page 24

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

9. SYSTEM CLOCKS
The master clock for the QF4A512 is produced by a crystal oscillator with a nominal frequency of 20MHz. Alternatively the device can
be fed with an external clock signal derived elsewhere. The master clock is used as a reference for a phase-locked loop (PLL), from
which clocks are derived to drive the FIR filters, the ADC and the analog front end. The master clock is also divided down to provide a
clock to be used for transfers to the on-chip EEPROM.
9.1 PLL Clock
The PLL clock frequency is determined by the input clock frequency, f
The default frequency for PLL_CLOCK is 200MHz. (f
Operation of the PLL is possible in two frequency ranges: 20-100MHz and 100-300MHz.
Control registers: PLL_CTRL0 and PLL_CTRL1
9.2 System Clock
The System Clock (SYS CLK) is divided down from PLL CLK by a number in the range 1 – 64, default = 1. SYS CLK is used as the
reference for the FIRs.
The default frequency for SYS CLK is 200MHz.
Control register: SYS_CLK_CTRL
9.3 ADC Clock
The ADC Clock (ADC CLK) is also divided down from PLL CLK. The range of divisor values is 2 -16, default = 2. ADC CLK is used to
drive the ADC (including CIC and CIH blocks) and other analog front end blocks.
The default frequency for ADC_CLK is 100MHz.
Control register: ADC_CLK_RATE
9.4 EE Clock
The EE Clock (EE CLK) is used for transfers to/from EEPROM. This clock is divided down directly from the master clock with divisors in
the range 1 – 32, default value = 16.
The default frequency for EE_CLK is 1.25MHz.
Control register: STARTUP
Rev C5, Jan 07
PLL_CLK = f
EXT CLK
XTAL or
0
* N / M
f
0
OSC
, 20MHz
PLL_CTRL0
(1 – 64)
Figure 7. System Clocks Block Diagram
/1
0
(Default settings shown)
= 20MHz, M = 1, N= 10)
Φ
PRELIMINARY
PLL
24
VCO
PLL_CTRL1
(1 – 64)
/10
0
, the pre-divider value (M) and the divider value (N):
200MHz
PLL_CLK
SYS_CLK_CTRL
ADC_CLK_RATE
STARTUP_1
(1 – 64)
(2 – 16)
(1 – 32)
/16
/1
/2
ADC_CLK
SYS_CLK
1.25MHz
200MHz
100MHz
EE_CLK
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QF4A512