qf4a512 ETC-unknow, qf4a512 Datasheet - Page 12

• Manufacturer Part Number: qf4a512
• Description: 4-channel Programmable Signal Converter Psc
• Manufacturer: ETC-unknow

3.3 Finite Impulse Response filter (FIR)
The four FIR filters consist of 512 taps each and are individually programmable. A different filter design may be implemented in each of
the 4 filters and may include lowpass, notched lowpass, highpass, bandpass, dual bandpass, bandstop, and dual bandstop. Currently
available filter algorithms include Parks-McLellan and Windowed Sinc.
3.4 Serial Interface - Serial Peripheral Interface (SPI)
The serial interface is fully compatible with a standard SPI bus. The serial bus on the QF4A512 is capable of running at up to 40 MHz,
although it may be run at much lower speeds. The QF4A512 operates in a SLAVE mode.
Two main modes of operation are used by the bus:
“Configure” mode is used to setup and program the QF4A512 Coefficient RAMs and control registers. Read access to the data RAMs is
also available.
“Run” mode provides up to 4 channels of 16-bit multiplexed data out the SPI port. The format is 24-bit (New Data Flag + Over Flow Info
+ Channel ID + 16-bits of data) multiplexed data. The chip will arbitrate between the incoming channels from the FIRs by monitoring
each channel's internal data ready signal. If new data for a given channel is ready in time, it will be inserted on the serial output stream
at the appropriate place for that channel and the new data flag will be set in the header. Otherwise the old data will remain in the time
slot and the new data flag will not be set. The highest channel sample rate is used as the data rate output for a Data Ready signal,
which can be used to maximize bus throughput.
3.5 Startup Modes
The behavior of the QF4A512 during power up or after a reset can be determined by the configuration of 2 bits in the STARTUP_1
register (07h). The auto_config bit, if set, will initiate transfer of EEPROM contents to the control registers and FIR filter coefficient
RAMs.
The auto_start bit will determine whether the chip starts in Run mode, filtering and sending data out on the SPI bus (auto_start=1), or
the chip will wait in configure mode until manually started (auto_start=0).
If the auto_config bit is not set, the chip will wait in configure mode until externally programmed.
An Extended Initialization mode is also available to perform sequences of data transfers from EEPROM to chip control registers (See
Chapter 5).
3.6 Memory
The QF4A512 features on-chip Control Registers, RAM and EEPROM. Important device configuration data and filter coefficients can be
copied to EEPROM to provide non-volatility. These data can be copied back from EEPROM when the chip is powered up making it
unnecessary to reprogram the device at each power up or reset.
Rev C5, Jan 07
The purpose of the CIH stage (not shown in block diagram) is the integration of 16 bits, and adjustment of the proper sample rate
through decimation. Gain correction and droop recovery is performed as well. After moving through the CIH, the signals are sent
into the FIR (Finite Impulse Response Filter) for user filtering.
Configure Mode
Serial Interface
Serial Interface
Run Mode
3FFF
0F00
2400
1000
0100
0000
RAM / REGISTERS
(no physical memory)
Control and Status
Registers (Sec 12)
Filter Coefficient
RAM (Sec 8.2)
Not Used
Not Used
Filter Data
(Sec 8.2)
Figure 2. Memory Map
PRELIMINARY
12
One to one
Mapping
0FFF
0F80
0F00
0100
0000
EEPROM (Sec 11)
Control and Status
Calibration Data
Filter Coefficient
(128 Bytes)
(128 bytes)
User Data
Data
Data
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QF4A512