saa6713h NXP Semiconductors, saa6713h Datasheet - Page 86

• Manufacturer Part Number: saa6713h
• Description: Xga Dual Input Flat Panel Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.17.8
The output interface has four global modes, which can be programmed with bits OI_enable, power_down and
blank_mode (register OI_CTRL0) according to Table 56.
The blank colour is programmable via bits blank_colour_red, blank_colour_green and blank_colour_blue.
Table 56 Global modes; note 1
Note
1. X = don’t care.
7.17.9
The output interface can handle single and double pixel
mode (bit double_pixel in register OI_CTRL1). In single
pixel mode one pixel (24 bits) is available each cycle at the
output ports. The panel clock PCLK is the same as the
back-end clock. In double pixel mode 2 pixels (48 bits) are
available at the output ports. The PCLK in double pixel
mode changes every second cycle of the back-end clock.
The panel clock polarity can be inverted by setting
PCLK_pol of register OI_CTRL1 to logic 1. At the
beginning of each frame the PCLK is synced again. It is
very important that the number of pixels in a double pixel
frame is even.
The horizontal sync signal of the selected video input
sources (DVI or VGA) may be used as a reference clock
for the panel PLL (see Table 57). This allows more stable
locking of the panel timing to the source timing. In this
mode the PLL will be ‘coasted’ during vertical sync when a
composite sync or sync-on-green is enabled
(iif_cs_sog_en = 1).
Table 57 Panel PLL
2004 Apr 05
enable
XGA dual input flat panel controller
OI_
X
1
0
1
pll_src
0
1
G
P
ANEL CLOCK
LOBAL CONTROL
power_
down
0
1
0
0
pre-divided clock
HS_PLL (iif_dvi_on = 0) or
HS_DVI (iif_dvi_on = 1)
blank_
mode
X
X
1
0
blank
Power-down
disable
normal
FUNCTION
MODE
all colours replaced by blank colour values
all registers set to default, like soft reset; all outputs LOW
all outputs reset but incoming data queued to trash
normal operation
86
7.17.10 H
Table 58 Starting output interface
STEP
1
2
3
4
5
OW TO START THE OUTPUT INTERFACE
set-up frame geometry
set-up signal generators
set-up wait column and wait mode
set-up PCLK and pixel mode
enable output interface
ACTION
ACTION
Product specification
SAA6713H