saa6713h NXP Semiconductors, saa6713h Datasheet - Page 53

• Manufacturer Part Number: saa6713h
• Description: Xga Dual Input Flat Panel Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
The picture generator consists of a border generation, a
vertical and a horizontal ramp and ripple generator, that
work independently. The two ramp and ripple generators
can be activated separately for each RGB colour
component. If h_ramp_r, h_ramp_g, h_ramp_b, v_ramp_r,
v_ramp_g or v_ramp_b are set to logic 1, the
corresponding ramp and ripple pattern is applied to the
corresponding colour component; otherwise the pattern
does not contribute to the colour component. If
white_border is logic 1, then the border generator is
activated for all colours. The border, horizontal and vertical
ramp and ripple generator outputs are added up for each
colour component. Additionally, all colour components are
bit reversed if invert is set to logic 1.
Both ramp and ripple pattern generators work in the same
way, only the horizontal generator is based on the column
position and the vertical generator on the line number. The
ramp and ripple generation is shown in Fig.14 for the
example of the horizontal generator.
The first step size (h_step1 or v_step1) defines the interval
after which the increment value (h_colour_inc or
v_colour_inc) is added to the current colour. If the second
step size (h_step2 or v_step2) is set to 0, the increment is
repeatedly added after the first step size interval. If the
second step size is not 0, after the increment value was
added the second step size defines the position where the
decrement value is subtracted from the current colour.
After this the first step size and the increment is applied
again and so on. Range over or underflows are not
suppressed and cause the colour values to wrap around.
2004 Apr 05
handbook, full pagewidth
XGA dual input flat panel controller
colour value
255
0
Fig.14 Picture generator ramp and ripple pattern (horizontal generator).
h_colour_inc
h_step1
h_step2
column position
53
7.9.6
For certain sampling phases the hsync is sampled at its
edge and thus unstable. This jitter is detected and another
sampling clock edge can be used to avoid it. To detect
hsync sample jitter the interval between hsyncs in sample
clock cycles is monitored. If the length varies, hsync jitter
is detected. As the sample jitter can only change the line
length by a maximum of two cycles, only the lowest two
bits of the line length have to be considered. If the current
line length differs from the previous line, line jitter occurred.
The differences of line lengths within a frame are
accumulated and the hsync jitter interrupt may be
generated when a certain level (hs_jitter_th) is exceeded.
During normal operation the jitter detection is only active
during the sampled area of the input frame, because the
clock rate of the PLL generated sample clock might slightly
vary during vsyncs. The detection circuit is active at all
times during reset or when the input interface is disabled.
For the interrupt a state and an enable register exists, as
well as a clear flag. The interrupt is level-based, so every
frame after a certain number of occurrences until the next
vsync the interrupt state is set to logic 1. The jitter
detection does not work correctly without a vsync signal.
h_colour_dec
H
SYNC JITTER DETECTION
Product specification
SAA6713H
wrap
around
MHC221