saa6712e NXP Semiconductors, saa6712e Datasheet - Page 43

• Manufacturer Part Number: saa6712e
• Description: Xga Rgb To Tft Graphics Engine
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.3
8.3.1
Sampling is done on the rising edge or on both edges of
VCLK depending on the number of ADCs.
The sample window is defined by v_offset, h_offset,
v_length, and h_length.
The offset counters start counting from the second edge of
their reference signals, i.e. VVS for vertical offset and VHS
for horizontal offset. Figure 10 shows the horizontal offset.
The polarities of the sync signals are given with vs_pol and
hs_pol. The vertical sample offset is given in lines and the
horizontal offset is measured in pixels. The width of the
sample window is defined by the length counters.
The vertical width is measured in lines and the horizontal
width in pixels, but only even pixel numbers are allowed.
The sample clock for the ADCs is always VCLK, but in dual
ADC mode this clock is half the pixel clock. Because of
that, in dual ADC mode, both clock edges are used to
sample data by the ADCs.
1999 Aug 25
handbook, full pagewidth
XGA RGB to TFT graphics engine
RGB input interface
RGB
RGB data
DATA SAMPLING
VHS
n
Fig.10 RGB data sampling.
h_offset
43
Table 8 Clock relationships
In single ADC mode, with each VCLK clock, a pixel must
be sampled from port A. In dual ADC mode, at each VCLK
clock edge, a pixel must be sampled alternating from
port A or B. The flag adc_sample_seq selects from which
port data sampling starts after the active edge of the
horizontal synchronization pulse.
8.3.2
The clamp pulse is generated with respect to half the dot
clock. The counters values responsible for switching the
clamp pulse on or off are clamp_on and clamp_off. Both
start counting from the second edge of VHS. The polarity
of CLAMP is given with clamp_pol.
NUMBER OF
0
ADCs
1
2
C
1
LAMP PULSE GENERATION
2 3 4 5
dot clock
1
2
dot clock
VCLK
h_length
Preliminary specification
SAA6712E
MHB253
positive
both
SAMPLE EDGE
VCLK