saa6712e NXP Semiconductors, saa6712e Datasheet - Page 41

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saa6712e

Manufacturer Part Number
saa6712e
Description
Xga Rgb To Tft Graphics Engine
Manufacturer
NXP Semiconductors
Datasheet
Philips Semiconductors
8.2.2
The pre- and post-dividers are implemented in such a way, that they support dividing ratios of 0.5 steps in an interval
from 1.5 to 10.5. All further dividing ratios are in steps of 1.0; see Fig.9 and Table 7.
Programming of the clock dividers must be done using the registers 26 to 32. It is necessary that the clock dividers must
be disabled before programming and be enabled afterwards. This can be done with pre_div_enable and
post_div_enable.
Table 7 Clock divider programming
1999 Aug 25
handbook, full pagewidth
handbook, full pagewidth
XGA RGB to TFT graphics engine
CLK/4.5
CLK/5.5
CLK/4
CLK/5
RATIO
C
CLK
1.5
2.0
2.5
3.0
3.5
LOCK DIVIDER
MCLKI
CLK
P-COUNTER
(HEX)
10
00
30
10
41
PRE-DIVIDER
Fig.9 Clock waveforms.
Fig.8 Clock generator.
N-COUNTER
PLL
(HEX)
32
10
00
30
10
41
41
POST-DIVIDER
2
COUNTER (HEX)
N-OFFSET
1
0
2
0
3
MHB251
Preliminary specification
MCLKO
PCLK
SAA6712E
HALF CLK
MHB252
1
0
1
1
1

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