sta333bwqs13tr STMicroelectronics, sta333bwqs13tr Datasheet - Page 61

• Manufacturer Part Number: sta333bwqs13tr
• Description: 2.1-channel High-efficiency Digital Audio System With Qsound Qhd
• Manufacturer: STMicroelectronics

STA333BWQS
7
7.1
7.2
Application
Application scheme for power supplies
Here in the next figure the typical application scheme for STA333BWQS concerning the
power supplies. A particular care has to be devoted to the layout of the PCB. In particular
the 3.3 Ω resistors on the digital supplies (VDD_DIG) have to be put as close as possible to
the device. This is to avoid any unwanted oscillation on the digital portion of the device due
to the PCB track inductance. The same rule must also be applied to all the decoulpling
capacitors in order to limit any kind of voltage spikes on all the supplies.
Figure 18. Application scheme for power supplies
PLL filter schematic
It is recommended to use the below scheme and values for the PLL loop filter to achieve the
best performances from the device in general application. Please be noted that the ground
of this filter scheme has to be conncted to the ground of the PLL without any resistive path.
Concerning the component values, please take into acount that the greater is the filter
bandwidth, the less is the lock time but the higher is the PLL output jitter.
Figure 19. PLL application scheme.
1000uF 35V
1000uF 35V
1000uF 35V
1000uF 35V
1uF 35V
1uF 35V
100nF
100nF
1uF 35V
1uF 35V
100nF
100nF
VCC
VCC
VCC
VCC
DDX3B
DDX3B
DDX3A
DDX3A
OUT2B
OUT2B
OUT2A
OUT2A
OUT2A
OUT2A
OUT1B
OUT1B
OUT1B
OUT1B
OUT1A
OUT1A
OUT1A
OUT1A
100nF
100nF
100nF
100nF
100nF
100nF
GND_DIG
GND_DIG
FILTER_PLL
FILTER_PLL
FILTER_PLL
FILTER_PLL
10
10
10
10
11
11
11
11
12
12
12
12
13
13
13
13
14
14
14
14
15
15
15
15
16
16
16
16
17
17
17
17
18
18
18
18
BEAD
BEAD
BEAD
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
GND_SUB
GND_SUB
GND_SUB
GND_SUB
SA
SA
SA
SA
TEST_MODE
TEST_MODE
TEST_MODE
TEST_MODE
VSS
VSS
VSS
VSS
VCC_REG
VCC_REG
VCC_REG
VCC_REG
OUT2B
OUT2B
OUT2B
OUT2B
GND2
GND2
GND2
GND2
VCC2
VCC2
VCC2
VCC2
OUT2A
OUT2A
OUT2A
OUT2A
OUT1B
OUT1B
OUT1B
OUT1B
VCC1
VCC1
VCC1
VCC1
GND1
GND1
GND1
GND1
OUT1A
OUT1A
OUT1A
OUT1A
GND_REG
GND_REG
GND_REG
GND_REG
VDD
VDD
VDD
VDD
CONFIG
CONFIG
CONFIG
CONFIG
DDX3B
DDX3B
DDX3B
DDX3B
DDX3A
DDX3A
DDX3A
DDX3A
2K2
2K2
2K2
2K2
4.7nF
4.7nF
4.7nF
4.7nF
FILTER_PLL
FILTER_PLL
FILTER_PLL
FILTER_PLL
TWARN/4A
TWARN/4A
TWARN/4A
TWARN/4A
GND_DIG
GND_DIG
GND_DIG
GND_DIG
PLL_GND
PLL_GND
PLL_GND
PLL_GND
GND_DIG
GND_DIG
GND_DIG
GND_DIG
VDD_DIG
VDD_DIG
VDD_DIG
VDD_DIG
VDD_PLL
VDD_PLL
VDD_PLL
VDD_PLL
VDD_DIG
VDD_DIG
VDD_DIG
VDD_DIG
INT_LINE
INT_LINE
INT_LINE
INT_LINE
EAPD/4B
EAPD/4B
EAPD/4B
EAPD/4B
PWRDN
PWRDN
PWRDN
PWRDN
RESET
RESET
RESET
RESET
LRCKI
LRCKI
LRCKI
LRCKI
BICKI
BICKI
BICKI
BICKI
100pF
100pF
100pF
100pF
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
SDI
SDI
SDI
SDI
XTI
XTI
XTI
XTI
36
36
36
36
35
35
35
35
34
34
34
34
33
33
33
33
32
32
32
32
31
31
31
31
30
30
30
30
29
29
29
29
28
28
28
28
27
27
27
27
26
26
26
26
25
25
25
25
24
24
24
24
23
23
23
23
22
22
22
22
21
21
21
21
20
20
20
20
19
19
19
19
PLL_GND
PLL_GND
3R3
3R3
680pF
680pF
680pF
680pF
PLL_FILT
PLL_FILT
PLL_FILT
PLL_FILT
TW
TW
EAPD
EAPD
3R3
3R3
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
INTL
INTL
DATA
DATA
DATA
DATA
LRCKI
LRCKI
BICKI
BICKI
XTI
XTI
100nF
100nF
100nF
100nF
PWDN
PWDN
GND_DIG
GND_DIG
100nF
100nF
100nF
100nF
BEAD
BEAD
BEAD
3V3
3V3
10K
10K
10K
10K
GND_DIG
GND_DIG
1nF
1nF
1nF
1nF
PLL_GND
PLL_GND
GND_DIG
GND_DIG
BEAD
BEAD
RESET
RESET
RESET
RESET
3V3
3V3
Application
3V3
3V3
3V3
3V3
RESET
RESET
RESET
RESET
GND_DIG
GND_DIG
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