sta333bwqs13tr STMicroelectronics, sta333bwqs13tr Datasheet - Page 30

• Manufacturer Part Number: sta333bwqs13tr
• Description: 2.1-channel High-efficiency Digital Audio System With Qsound Qhd
• Manufacturer: STMicroelectronics

Register description
6.2.4
6.2.5
30/71
Table 20.
Delay serial clock enable
Table 21.
Channel input mapping
Table 22.
Each channel received via I
Channel Input Mapping registers. This allows for flexibility in processing. The default
settings of these registers map each I
channel.
Bit
Bit
5
6
7
BICKI
64fs
R/W
R/W
R/W
R/W
R/W
Supported serial audio input formats for LSB-first (SAIFB = 1) (continued)
Delay serial clock enable
Channel input mapping
RST
RST
0
0
1
SAI [3:0]
0000
0100
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
2
S can be mapped to any internal processing channel via the
DSCKE
Name
Name
C1IM
C2IM
SAIFB
2
1
1
1
1
1
1
1
1
1
1
1
1
S input channel to its corresponding processing
0: processing channel 1 receives Left I
1: processing channel 1 receives Right I
0: processing channel 2 receives Left I
1: processing channel 2 receives Right I
0: no serial clock delay
1: serial clock delay by 1 core clock cycle to tolerate
anomalies in some I2S master devices
I
I
I
LSB first I
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
2
2
2
S 24-bit data
S 20-bit data
S 18-bit data
2
S 16-bit data
Interface Format
Description
Description
STA333BWQS
2
2
S Input
S Input
2
2
S Input
S Input