sta335bws13tr STMicroelectronics, sta335bws13tr Datasheet - Page 67

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sta335bws13tr

Manufacturer Part Number
sta335bws13tr
Description
2.1-channel 40-watt High-efficiency Digital Audio System Sound Terminal?
Manufacturer
STMicroelectronics
Datasheet

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STA369BWS
6.13
6.13.1
Extended configuration register (addr 0x36)
Extended configuration register provides access to B
Dual-band DRC (B
STA369BWS device provide a dual-band DRC (B
path, as depicted in
Figure 19. B
The low frequency information (LFE) is extracted from left and right channels, removing the
high frequencies using a programmable biquad filter, and then computing the difference with
the original signal. Limiter 1 (DRC1) is then used to control left/right high frequency
components amplitude while limiter 2 (DRC2) is used to control the low frequency
components (see
The cut-off frequency of the high pass filters can be user defined, XO[3:0] = 0, or selected
from the predefined values.
DRC1 and DRC2 are then used to independently limit L/R high frequencies and LFE
channels amplitude (see
this configuration, the dedicated channel 3 volume control can be actually acted as a bass
boost enhancer as well (0.5 dB/step resolution).
The processed LFE channel is then recombined with the L and R channels in order to
reconstruct the 2.0 output signal.
Sub-band decomposition
The sub-band decomposition for B
The cut off frequency can be programmed in two ways, using XO bits in register 0x0C, or
using “user programmable” mode (coefficients stored in RAM addresses 0x28 to 0x31).
MDRC[1]
D7
0
R
R
R
R
L
L
L
L
MDRC[0]
2
DRC scheme
D6
0
Chapter
Figure
2
DRC)
Chapter
PS48DB
6.6).
19. Dual-band DRC is activated by setting MDRC[1:0] = 1x.
D5
0
Doc ID 16861 Rev 3
Pass
Pass
Hi-pass
Hi-pass
Pass
Pass
Hi-pass
Hi-pass
B
B
B
B
Filter
Filter
Filter
Filter
2
2
filter
filter
2
2
filter
filter
DRC
DRC
DRC
DRC
6.6) as well as their volume control. To be noted that, in
2
DRC can be configured specifying the cutoff frequency.
XO
XO
XO
XO
XAR1
D4
0
-
-
-
-
2
XAR2
DRC) on the left and right channels data
D3
0
2
DRC and biquad 5, 6 and 7.
Volume
Volume
Volume
Volume
Volume
Volume
Volume
Volume
CH1
CH1
CH3
CH3
CH3
CH3
CH2
CH2
BQ5
D2
0
DRC1
DRC1
DRC2
DRC2
DRC2
DRC2
DRC1
DRC1
Limiter
Limiter
Limiter
Limiter
Limiter
Limiter
Register description
And
And
And
And
And
And
Vol
Vol
Vol
Vol
Vol
Vol
BQ6
D1
0
+
+
+
+
BQ7
D0
0
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