sab9076h NXP Semiconductors, sab9076h Datasheet - Page 9

• Manufacturer Part Number: sab9076h
• Description: Picture-in-picture Pip Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
Pixel rate
The internal chrominance format used is 4 : 1 : 1. It is
expected that the bandwidth of the input signals is limited
to 4.5 MHz for the Y input and 1.125 MHz for the U/V input.
The Y input is sampled with a 1728
clock and is filtered and down sampled to the internal
864
The U and V inputs are multiplexed and sampled with a
432
216
Acquisition area
Synchronisation is achieved via the acquisition H
V
system constant the starting point of the acquisition can be
controlled.
The acquisition area is 672 pixels/line and 228 lines/field
for NTSC. Both main and sub-channels are equivalent in
handling the data.
Table 2 PIP sizes
1996 Aug 13
Pixels
Lines
sync
REDUCTION
Picture-In-Picture (PIP) controller
pins. With the acquisition fine positioning added to a
HS ( 13.5 MHz) pixel rate.
HS clock and down sampled to the internal
HS ( 3.375 MHz) pixel rate.
672
H/1
336
H/2
HS ( 27.0 MHz)
224
H/3
Sync
and
9
168
H/4
Display mode
The internal display pixel rate is 864
13.5 MHz. This pixel rate is up sampled by interpolation to
1728
Display area
The display background is an area of 696 pixels and
238 lines. This can be put on/off by the BGON bit
independent of the PIPON bit. This area can be moved by
the display background fine positioning (BGHFP and
BGVFP registers). Its colour is determined by the BGCOL
and BGBRT registers.
Within this area PIPs are defined dependent on the PIP
mode. The PIP sizes are determined by the display
reduction factors as is shown in Table 2.
The display fine positioning determines the location of the
PIPs with respect to the background. Sub-channel and
main channel both have their independent PIP size and
location control, which is shown in Fig.3.
DPH
228
V/1
sync
before the DAC stage.
114
V/2
Preliminary specification
V/3
76
SAB9076H
DPH
sync
which is
V/4
57