at89c51cc03c-slsim ATMEL Corporation, at89c51cc03c-slsim Datasheet - Page 65

• Manufacturer Part Number: at89c51cc03c-slsim
• Description: At89c51cc03 Enhanced 8-bit Mcu With Can Controller And Flash Memory
• Manufacturer: ATMEL Corporation

Registers
4182N–CAN–03/08
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Table 25. SCON Register
SCON (S:98h)
Serial Control Register
Reset Value = 0000 0000b
Bit addressable
Number
FE/SM0
Bit
7
7
6
5
4
3
2
1
0
Mnemonic Description
SM1
REN
SM0
SM1
SM2
RB8
TB8
Bit
FE
6
TI
RI
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
Serial port Mode bit 0 (SMOD0=0)
Refer to SM1 for serial port mode selection.
Serial port Mode bit 1
SM0
0
0
1
1
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 33. and
Figure 34. in the other modes.
SM2
5
SM1
0
1
0
1
REN
Mode
Shift Register F
8-bit UART
9-bit UART
9-bit UART
4
TB8
3
Baud Rate
Variable
F
Variable
XTAL
XTAL
/12 (or F
/64 or F
RB8
XTAL
2
XTAL
/32
/6 in mode X2)
TI
1
RI
0
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