at89c51cc03c-slsim ATMEL Corporation, at89c51cc03c-slsim Datasheet - Page 42
at89c51cc03c-slsim
Manufacturer Part Number
at89c51cc03c-slsim
Description
At89c51cc03 Enhanced 8-bit Mcu With Can Controller And Flash Memory
Manufacturer
ATMEL Corporation
Datasheet
1.AT89C51CC03C-SLSIM.pdf
(197 pages)
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Figure 22. External Code Fetch Waveforms
Flash Memory
Architecture
Figure 23. Flash Memory Architecture with ENBOOT=1 (boot mode)
42
AT89C51CC03
Extra Row (128 Bytes)
Hardware Security (1 byte)
Column Latches (128 Bytes)
CPU Clock
PSEN#
ALE
P0
P2
D7:0
PCH
AT89C51CC03 features two on-chip Flash memories:
•
•
The FM0 can be program by both parallel programming and Serial In-System Program-
ming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP
mode is detailed in the "In-System Programming" section.
All Read/Write access operations on Flash Memory by user application are managed by
a set of API described in the "In-System Programming" section.
The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh. Figure
23 and Figure 24 show the Flash memory configuration with ENBOOT=1 and
ENBOOT=0.
FFFFh
F800h
0000h
Flash memory FM0:
containing 64K Bytes of program memory (user space) organized into 128 byte
pages,
Flash memory FM1:
2K Bytes for boot loader and Application Programming Interfaces (API).
PCL
64K Bytes
FM0
PCH
Memory space not accessible
D7:0
FM1 mapped between FFFFh and
F800h when bit ENBOOT is set in
AUXR1 register
PCL
Flash memory
boot space
2K Bytes
FM1
PCH
D7:0
FFFFh
F800h
4182N–CAN–03/08
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